A 1.5-V DRAM for battery-based applications. - Masakazu Aoki; Jun Etoh; Kiyoo Itoh 001; Shin Kimura; Yoshifumi Kawamoto (IEEE J. Solid State Circuits, 1989)

A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier. - Masashi Horiguchi; Masakazu Aoki; Jun Etoh; Hitoshi Tanaka; Shin'ichi Ikenaga; Kiyoo Itoh 001; Kazuhiko Kajigaya; Hiroaki Kotani; Kazuyoshi Ohshima; Tetsuro Matsumoto (IEEE J. Solid State Circuits, 1990)

A flexible redundancy technique for high-density DRAMs. - Masashi Horiguchi; Jun Etoh; Masakazu Aoki; Kiyoo Itoh 001; Tetsuro Matsumoto (IEEE J. Solid State Circuits, 1991)

Dual-regulator dual-decoding-trimmer DRAM voltage limiter for burn-in test. - Masashi Horiguchi; Masakazu Aoki; Jun Etoh; Gyoo Itoh; Kazuhiko Kajigaya; Atsushi Nozoe; Tetsuro Matsumoto (IEEE J. Solid State Circuits, 1991)

Sub-1-μA dynamic reference voltage generator for battery-operated DRAMs. - Hitoshi Tanaka; Yoshinobu Nakagome; Jun Etoh; Eiji Yamasaki; Masakazu Aoki; Kazuyuki Miyazawa (IEEE J. Solid State Circuits, 1994)

A 29-mm2, 1.8-V-only, 16-Mb DINOR flash memory with gate-protected-poly-diode (GPPD) charge pump. - Yoshikazu Miyawaki; Osamu Ishizaki; Yoshihiko Okihara; Tsutomu Inaba; Fumihiko Nitta; Masaaki Mihara; Takashi Hayasaka; Kazuo Kobayashi; Tadashi Omae; Hiroshi Kimura; Satoshi Shimizu; Hiromi Makimoto; et al. (IEEE J. Solid State Circuits, 1999)

Multi-Scale Active Vibration Suppression Technology for Nanometer-Order System. - Jun Etoh; Hironori Ogawa; Hiroki Takahashi (SII, 2024)