An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity. - Jun Furuta; Kazutoshi Kobayashi; Hidetoshi Onodera (IEICE Trans. Electron., 2010)

A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles. - Jun Furuta; Chikara Hamanaka; Kazutoshi Kobayashi; Hidetoshi Onodera (ASP-DAC, 2011)

Correlations between well potential and SEUs measured by well-potential perturbation detectors in 65nm. - Jun Furuta; Ryosuke Yamamoto; Kazutoshi Kobayashi; Hidetoshi Onodera (A-SSCC, 2011)

Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures. - Chikara Hamanaka; Ryosuke Yamamoto; Jun Furuta; Kanto Kubota; Kazutoshi Kobayashi; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

A Radiation-Hard Redundant Flip-Flop to Suppress Multiple Cell Upset by Utilizing the Parasitic Bipolar Effect. - Kuiyuan Zhang; Jun Furuta; Ryosuke Yamamoto; Kazutoshi Kobayashi; Hidetoshi Onodera (IEICE Trans. Electron., 2013)

Impact of Cell Distance and Well-contact Density on Neutron-induced Multiple Cell Upsets. - Jun Furuta; Kazutoshi Kobayashi; Hidetoshi Onodera (IEICE Trans. Electron., 2015)

Circuit-level simulation methodology for Random Telegraph Noise by using Verilog-AMS. - Takuya Komawaki; Michitarou Yabuuchi; Ryo Kishida; Jun Furuta; Takashi Matsumoto; Kazutoshi Kobayashi (ICICDT, 2017)

Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS Model. - Takuya Komawaki; Michitarou Yabuuchi; Ryo Kishida; Jun Furuta; Takashi Matsumoto; Kazutoshi Kobayashi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Sensitivity to soft errors of NMOS and PMOS transistors evaluated by latches with stacking structures in a 65 nm FDSOI process. - Kodai Yamada; Haruki Maruoka; Jun Furuta; Kazutoshi Kobayashi (IRPS, 2018)

A Low-Power Radiation-Hardened Flip-Flop with Stacked Transistors in a 65 nm FDSOI Process. - Haruki Maruoka; Masashi Hifumi; Jun Furuta; Kazutoshi Kobayashi (IEICE Trans. Electron., 2018)

Temperature Dependence of Bias Temperature Instability (BTI) in Long-term Measurement by BTI-sensitive and -insensitive Ring Oscillators Removing Environmental Fluctuation. - Takuya Asuke; Ryo Kishida; Jun Furuta; Kazutoshi Kobayashi (ASICON, 2019)

Soft-Error Tolerance Depending on Supply Voltage by Heavy Ions on Radiation-Hardened Flip Flops in a 65 nm Bulk Process. - Yuto Tsukita; Mitsunori Ebara; Jun Furuta; Kazutoshi Kobayashi (ASICON, 2019)

Comparison of Radiation Hardness of Stacked Transmission-Gate Flip Flop and Stacked Tristate-Inverter Flip Flop in a 65 nm Thin BOX FDSOI Process. - Mitsunori Ebara; Kodai Yamada; Jun Furuta; Kazutoshi Kobayashi (IOLTS, 2019)

Total Ionizing Dose Effects by alpha irradiation on circuit performance and SEU tolerance in thin BOX FDSOI process. - Takashi Yoshida; Kazutoshi Kobayashi; Jun Furuta (IOLTS, 2019)

Impact of Combinational Logic Delay for Single Event Upset on Flip Flops in a 65 nm FDSOI Process. - Jun Furuta; Yuto Tsukita; Kodai Yamada; Mitsunori Ebara; Kentaro Kojima; Kazutoshi Kobayashi (IRPS, 2019)

An Accurate Device-Level Simulation Method to Estimate Cross Sections of Single Event Upsets by Silicon Thickness in Raised Layer. - Kentaro Kojima; Kodai Yamada; Jun Furuta; Kazutoshi Kobayashi (IRPS, 2019)

Monolithic integration of gate driver and p-GaN power HEMT for MHz-switching implemented by e-mode GaN-on-SOI process. - Yuki Yamashita; Steve Stoffels; Niels Posthuma; Karen Geens; Xiangdong Li; Jun Furuta; Stefaan Decoutere; Kazutoshi Kobayashi (IEICE Electron. Express, 2019)

Characterizing SRAM and FF soft error rates with measurement and simulation. - Masanori Hashimoto; Kazutoshi Kobayashi; Jun Furuta; Shin-ichiro Abe; Yukinobu Watanabe (Integr., 2019)

Evaluation of Heavy-Ion-Induced Single Event Upset Cross Sections of a 65-nm Thin BOX FD-SOI Flip-Flops Composed of Stacked Inverters. - Kentaro Kojima; Kodai Yamada; Jun Furuta; Kazutoshi Kobayashi (IEICE Trans. Electron., 2020)

An E-mode p-GaN HEMT monolithically-integrated three-level gate driver operating with a single voltage supply. - Junichiro Nagao; Urmimala Chatterjee; Xiangdong Li; Jun Furuta; Stefaan Decoutere; Kazutoshi Kobayashi (IEICE Electron. Express, 2021)

Radiation Hardened Flip-Flops Minimizing Area, Power, and Delay Overheads with 1/100 Lower α-SER in a 130 nm Bulk Process. - Ryuichi Nakajima; Kazuya Ioki; Jun Furuta; Kazutoshi Kobayashi (IOLTS, 2022)

Frequency Dependency of Soft Error Rates Based on Dynamic Soft Error Measurements. - Haruto Sugisaki; Ryuichi Nakajima; Shotaro Sugitani; Jun Furuta; Kazutoshi Kobayashi (ICICDT, 2023)

SEU Sensitivity of PMOS and NMOS Transistors in a 65 nm Bulk Process by α-Particle Irradiation. - Keita Yoshida; Ryuichi Nakajima; Shotaro Sugitani; Takafumi Ito; Jun Furuta; Kazutoshi Kobayashi (ICICDT, 2023)

Radiation Hardness Evaluations of a Stacked Flip Flop in a 22 nm FD-SOI Process by Heavy-Ion Irradiation. - Shotaro Sugitani; Ryuichi Nakajima; Takafumi Ito; Jun Furuta; Kazutoshi Kobayashi; Mathieu Louvat; Francois Jacquet; Jean-Christophe Eloy; Olivier Montfort; Lionel Jure; Vincent Huard (IOLTS, 2023)

Ultra Long-term Measurement Results of BTI-induced Aging Degradation on 7-nm Ring Oscillators. - Kazutoshi Kobayashi; Tomoharu Kishita; Hiroki Nakano; Jun Furuta; Mitsuhiko Igarashi; Shigetaka Kumashiro; Michitarou Yabuuchi; Hironori Sakamoto (IRPS, 2023)

Radiation Hardened Flip-Flops with low Area, Delay and Power Overheads in a 65 nm bulk process. - Shotaro Sugitani; Ryuichi Nakajima; Keita Yoshida; Jun Furuta; Kazutoshi Kobayashi (IRPS, 2023)

A Partially-redundant Flip-flip Suitable for Mitigating Single Event Upsets in a FD-SOI Process with Low Performance Overhead. - Jun Furuta; Shotaro Sugitani; Ryuichi Nakajima; Kazutoshi Kobayashi (IRPS, 2024)

An Approach to Neutron-Induced SER Evaluation Using a Clinical 290 MeV/ u Carbon Beam and Particle Transport Simulations. - Ryuichi Nakajima; Shotaro Sugitani; Haruto Sugisaki; Takafumi Ito; Jun Furuta; Kazutoshi Kobayashi; Makoto Sakai (IRPS, 2024)

Frequency dependence of soft error rates induced by alpha-particle and heavy ion. - Haruto Sugisaki; Ryuichi Nakajima; Shotaro Sugitani; Jun Furuta; Kazutoshi Kobayashi (IEICE Electron. Express, 2024)

Measuring SET Pulse Widths in pMOSFETs and nMOSFETs Separately by Heavy Ion and Neutron Irradiation. - Jun Furuta; Shotaro Sugitani; Ryuichi Nakajima; Takafumi Ito; Kazutoshi Kobayashi (IEICE Trans. Electron., 2024)

Soft-Error Tolerance by Guard-Gate Structures on Flip-Flops in 22 and 65 nm FD-SOI Technologies. - Ryuichi Nakajima; Takafumi Ito; Shotaro Sugitani; Tomoya Kii; Mitsunori Ebara; Jun Furuta; Kazutoshi Kobayashi; Mathieu Louvat; Francois Jacquet; Jean-Christophe Eloy; Olivier Montfort; Lionel Jure; et al. (IEICE Trans. Electron., 2024)

Radiation-Hardened Flip-Flops in a 65 nm Bulk Process for Terrestrial Applications Coping with Radiation Hardness and Performance Overheads. - Shotaro Sugitani; Ryuichi Nakajima; Keita Yoshida; Jun Furuta; Kazutoshi Kobayashi (IEICE Trans. Electron., 2025)