A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture. - Kibong Koo; Sunghwa Ok; Yonggu Kang; Seungbong Kim; Choungki Song; Hyeyoung Lee; Hyungsoo Kim; Yongmi Kim; Jeonghun Lee; Seunghan Oak; Yosep Lee; Jungyu Lee 002; et al. (ISSCC, 2012)

22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme. - Chi-Sung Oh; Ki Chul Chun; Young-Yong Byun; Yong-Ki Kim; So-Young Kim; Yesin Ryu; Jaewon Park; Sinho Kim; Sang-uhn Cha; Dong-Hak Shin; Jungyu Lee 002; Jong-Pil Son; et al. (ISSCC, 2020)

A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme. - Ki Chul Chun; Yong-Ki Kim; Yesin Ryu; Jaewon Park; Chi Sung Oh; Young-Yong Byun; So-Young Kim; Dong-Hak Shin; Jun Gyu Lee 002; Byung-Kyu Ho; Min-Sang Park; Seong-Jin Cho; et al. (IEEE J. Solid State Circuits, 2021)

A 1Tb 3b/Cell 8th-Generation 3D-NAND Flash Memory with 164MB/s Write Throughput and a 2.4Gb/s Interface. - Moosung Kim; Sung-Won Yun; Jungjune Park; Hyun Kook Park; Jungyu Lee 002; Yeong Seon Kim; Dae-Hoon Na; Sara Choi; Youngsun Song; Jonghoon Lee; Hyun-Jun Yoon; Kangbin Lee; et al. (ISSCC, 2022)

A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features. - Yesin Ryu; Young-Cheon Kwon; Jaehoon Lee 005; Sung-Gi Ahn; Jaewon Park; Kijun Lee; Yu Ho Choi; Han-Won Cho; Jae San Kim; Jungyu Lee 002; Haesuk Lee; Seung Ho Song; et al. (VLSI Technology and Circuits, 2022)

A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features. - Yesin Ryu; Sung-Gi Ahn; Jaehoon Lee 005; Jaewon Park; Yong-Ki Kim; Hyochang Kim; Yeong Geol Song; Han-Won Cho; Sunghye Cho; Seung Ho Song; Haesuk Lee; Useung Shin; et al. (IEEE J. Solid State Circuits, 2023)