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Jun Gyu Lee

Affiliations:
  • Tohoku University, Research Institute of Electrical Communication, Sendai, Japan


According to our database1, Jun Gyu Lee authored at least 6 papers between 2011 and 2012.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

On csauthors.net:

Bibliography

2012
Loop Design Optimization of Fourth-Order Fractional-N PLL Frequency Synthesizers.
[BibTeX]
[DOI]
Jun Gyu Lee
,
Zule Xu
,
Shoichi Masui
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

A 32-bit 16-program-cycle nonvolatile memory for analog circuit calibration in a standard 0.18µm CMOS.
[BibTeX]
[DOI]
Jun Gyu Lee
,
Shoichi Masui
IEICE Electron. Express, 2012

A 3.5mW 5µsec settling time dual-band fractional-N PLL synthesizer.
[BibTeX]
[DOI]
Jun Gyu Lee
,
Shoichi Masui
IEICE Electron. Express, 2012

Fractional-N PLL synthesizer with 15µsec start-up time by on-chip nonvolatile memory.
[BibTeX]
[DOI]
Jun Gyu Lee
,
Shoichi Masui
IEICE Electron. Express, 2012

2011
Self-Dithered Digital Delta-Sigma Modulators for Fractional-N PLL.
[BibTeX]
[DOI]
Zule Xu
,
Jun Gyu Lee
,
Shoichi Masui
IEICE Trans. Electron., 2011

Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using <i>g<sub>m</sub></i>/<i>I<sub>D</sub></i> Lookup Table Methodology.
[BibTeX]
[DOI]
Takayuki Konishi
,
Kenji Inazu
,
Jun Gyu Lee
,
Masanori Natsui
,
Shoichi Masui
,
Boris Murmann
IEICE Trans. Electron., 2011


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