Jun Han

According to our database1, Jun Han authored at least 69 papers between 2006 and 2020.

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2020
A Power Analysis Attack Resistant Multicore Platform With Effective Randomization Techniques.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Radiation-Hardened 0.3-0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2020

VPQC: A Domain-Specific Vector Processor for Post-Quantum Cryptography Based on RISC-V Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant Circuit.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
A Real-Time and Hardware-Efficient Processor for Skeleton-Based Action Recognition With Lightweight Convolutional Neural Network.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A Skeleton-based Action Recognition System for Medical Condition Detection.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

A Hardware-efficient Accelerator for Encoding Stage of Text-to-speech Synthesis.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
Countering power analysis attacks by exploiting characteristics of multicore processors.
IEICE Electron. Express, 2018

The Hardware Acceleration of SC Decoder for Polar Code towards HLS Optimization.
Proceedings of the International SoC Design Conference, 2018

MiniTracker: A Lightweight CNN-based System for Visual Object Tracking on Embedded Device.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

2017
A multi-core-based heterogeneous parallel turbo decoder.
IEICE Electron. Express, 2017

Instruction set extension and hardware acceleration for SVM application toward a vector processor.
Proceedings of the International SoC Design Conference, 2017

FPGA-based efficient implementation of SURF algorithm.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

Parallel implementations of SHA-3 on a 24-core processor with software and hardware co-design.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

Fp<sup>2</sup> arithmetic acceleration based on modified Barrett modular multiplication algorithm.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

A high utilization FPGA-based accelerator for variable-scale convolutional neural network.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

A configurable nonlinear operation unit for neural network accelerator.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
An Area-Efficient Error-Resilient Ultralow-Power Subthreshold ECG Processor.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Cryptographie coprocessor design for IoT sensor nodes.
Proceedings of the International SoC Design Conference, 2016

A low-cost and energy-efficient EEG processor for continuous seizure detection using wavelet transform and AdaBoost.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

2015
Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A 65 nm Cryptographic Processor for High Speed Pairing Computation.
IEEE Trans. Very Large Scale Integr. Syst., 2015

An Energy-Efficient Design for ECG Recording and R-Peak Detection Based on Wavelet Transform.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

A Heterogeneous Multicore Crypto-Processor With Flexible Long-Word-Length Computation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 1.5-D Multi-Channel EEG Compression Algorithm Based on NLSPIHT.
IEEE Signal Process. Lett., 2015

A configurable SoC design for information security.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A low-cost SoC implementation of AES algorithm for bio-signals.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Parallel implementation of AES on 2.5D multicore platform with hardware and software co-design.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A SIMD multiplier-accumulator design for pairing cryptography.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Motion artifact removal based on ICA for ambulatory ECG monitoring.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A lifting-based 2-D discrete wavelet transform architecture for data compression of bio-potential signals.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Exploration for energy-efficient ECC decoder of WBAN.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
An Efficient Implementation of Montgomery Multiplication on Multicore Platform With Optimized Algorithm, Task Partitioning, and Network Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2014

A 16-Core Processor With Shared-Memory and Message-Passing Communications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing.
IEICE Electron. Express, 2014

An error-resilient wavelet-based ECG processor under voltage overscaling.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

2013
Parallelization of Radix-2 Montgomery Multiplication on Multicore Platform.
IEEE Trans. Very Large Scale Integr. Syst., 2013

An Ultra-Low Power QRS Complex Detection Algorithm Based on Down-Sampling Wavelet Transform.
IEEE Signal Process. Lett., 2013

Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65 nm CMOS.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Robustness Analysis of Mesh-Based Network-on-Chip Architecture under Flooding-Based Denial of Service Attacks.
Proceedings of the IEEE Eighth International Conference on Networking, 2013

A 920MHz quad-core cryptography processor accelerating parallel task processing of public-key algorithms.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

A highly energy-efficient compressed sensing encoder with robust subthreshold clockless pipeline for wireless BANs.
Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013

Low power design for FIR filter.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

An extensible and real-time compressive sensing reconstruction hardware for WBANs using OMP.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Highly flexible WBAN transmit-receive system based on USRP.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Design of a high throughput configurable variable-length FFT processor based on switch network architecture.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

An ultra low-power and area-efficient baseband processor for WBAN transmitter.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2013

A hardware-efficient variable-length FFT processor for low-power applications.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2013

2012
A High Speed Reconfigurable Face Detection Architecture Based on AdaBoost Cascade Algorithm.
IEICE Trans. Inf. Syst., 2012

Design Approach and Implementation of Application Specific Instruction Set Processor for SHA-3 BLAKE Algorithm.
IEICE Trans. Electron., 2012

A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS.
IEICE Electron. Express, 2012

A low power ASIP for precision configurable FFT processing.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2012

2011
Design of a single-ended cell based 65nm 32×32b 4R2W register file.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A security processor based on MIPS 4KE architecture.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Analysis of adaptive support-weight based stereo matching for hardware realization.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A NoC-based multi-core architecture for IEEE 802.11i CCMP.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A control scheme for a 65nm 32×32b 4-read 2-write register file.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
Optimized digital automatic gain control for DVB-S2 system.
Proceedings of the 2010 Wireless Telecommunications Symposium, 2010

Robust and reliable frame synchronization method for DVB-S2 system.
Proceedings of the 2010 Wireless Telecommunications Symposium, 2010

2009
A multi-task-oriented security processing architecture with powerful extensibility.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Tracking loop for IR-UWB communications in IEEE 802.15 multi-path channels.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Optimal frame synchronization for DVB-S2.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A full-custom design of AES SubByte module with signal independent power consumption.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A low-cost cryptographic processor for security embedded system.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Two-dimensional Parity-based Concurrent Error Detection Method for AES Algorithm against Differential Fault Attack and its VLSI Implementation.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

An Energy-Proportion Synchronization Method for IR-UWB Communications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Low-cost and High-performance SoC Design for OMA DRM2 Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
A high-performance platform-based SoC for information security.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006


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