Jun Han
Orcid: 0000-0002-5245-0754Affiliations:
- Fudan University, State Key Laboratory of ASIC and System, Shanghai, China
According to our database1,
Jun Han
authored at least 109 papers
between 2006 and 2024.
Collaborative distances:
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Bibliography
2024
A 1.6 GS/s 42.6-dB SNDR Synthesis Friendly Time-Interleaved SAR ADC Using Metastability Detection and Escape Acceleration Technique.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024
SET Tolerable SRAM Hardened by DMR Circuit With Feedback-Split-Gate Voter and High-Speed Hierarchical Structure.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
An Energy-Efficient BNN Accelerator With Two-Stage Value Prediction for Sparse-Edge Gesture Recognition.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024
2023
Dominant-Node Theory and Monitoring-Rescue Method for Eliminating Undesired Operating Points in the Self-Biased Reference Generators.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
DMBF: Design Metrics Balancing Framework for Soft-Error-Tolerant Digital Circuits Through Bayesian Optimization.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023
UArch: A Super-Resolution Processor With Heterogeneous Triple-Core Architecture for Workloads of U-Net Networks.
IEEE Trans. Biomed. Circuits Syst., June, 2023
A Non-Redundant Latch With Key-Node-Upset Obstacle of Beneficial Efficiency for Harsh Environments Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2023
SPARK: An automatic Score-Power-Area efficient RISC-V processor microarchitecture SeeKer.
Microelectron. J., February, 2023
A foreground digital calibration algorithm for time-interleaved ADCs with low computational complexity.
Microelectron. J., 2023
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
A Self Bias-flip Piezoelectric Energy Harvester Array without External Energy Reservoirs achieving 488% Improvement with 4-Ratio Switched-PEH DC-DC Converter.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
General Vector Instruction Extension for GF(2<sup>m</sup>) Polynomial Operation in Post-quantum Cryptography.
Proceedings of the 15th IEEE International Conference on ASIC, 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
Enhancing RISC-V Vector Extension for Efficient Application of Post-Quantum Cryptography.
Proceedings of the 34th IEEE International Conference on Application-specific Systems, 2023
2022
LosaTM: A Hardware Transactional Memory Integrated With a Low-Overhead Scenario-Awareness Conflict Manager.
IEEE Trans. Parallel Distributed Syst., 2022
A High-Performance Domain-Specific Processor With Matrix Extension of RISC-V for Module-LWE Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
An Enhanced Start-up Circuit Eliminating All Trojan States in Self-biased Reference Generators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A Synthesis Friendly Dynamic Amplifier with Fuzzy-Logic Piecewise-Linear Calibration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A Cross Regulation Reduced Multi-Output and Multi-VCR Piezoelectric Energy Harvesting System Using Shared Capacitors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A High-Speed NTT-Based Polynomial Multiplication Accelerator with Vector Extension of RISC-V for Saber Algorithm.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
2021
An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
DyGA: A Hardware-Efficient Accelerator With Traffic-Aware Dynamic Scheduling for Graph Convolutional Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Radiation Hardened 12T SRAM With Crossbar-Based Peripheral Circuit in 28nm CMOS Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
MC-LSTM: Real-Time 3D Human Action Detection System for Intelligent Healthcare Applications.
IEEE Trans. Biomed. Circuits Syst., 2021
A 28 nm, 397 μW real-time dynamic gesture recognition chip based on RISC-V processor.
Microelectron. J., 2021
Microelectron. J., 2021
A hardware-efficient dual-source data replication and local broadcast mechanism in distributed shared caches.
Microelectron. J., 2021
A Heterogeneous Full-stack AI Platform for Performance Monitoring and Hardware-specific Optimizations.
Proceedings of the 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2021
A Multi-Layer Parallel Hardware Architecture for Homomorphic Computation in Machine Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
TRIGON: A Single-phase-clocking Low Power Hardened Flip-Flop with Tolerance to Double-Node-Upset for Harsh Environments Applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
A Synthesizable 0.0060mm<sup>2</sup> VCO-Based Delta Sigma Modulator with Digital Tri-level Feedback Scheme.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
Mini-HOG: An Area-efficient and Low-power HOG Accelerator with SW/HW co-design for Real-time Pedestrian Detection.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
Proceedings of the 14th IEEE International Conference on ASIC, 2021
An Energy-Efficient Image Denoising Accelerator with Depth-wise Separable Convolution and Fused-Layer Architecture.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
2020
A Power Analysis Attack Resistant Multicore Platform With Effective Randomization Techniques.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Radiation-Hardened 0.3-0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2020
VPQC: A Domain-Specific Vector Processor for Post-Quantum Cryptography Based on RISC-V Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
An Optimization Toolchain Design of Deep Learning Deployment Based on Heterogeneous Computing Platform.
Proceedings of the 2020 International Conference on Wireless Communications and Signal Processing (WCSP), 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant Circuit.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
A Real-Time and Hardware-Efficient Processor for Skeleton-Based Action Recognition With Lightweight Convolutional Neural Network.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
Countering power analysis attacks by exploiting characteristics of multicore processors.
IEICE Electron. Express, 2018
Proceedings of the International SoC Design Conference, 2018
MiniTracker: A Lightweight CNN-based System for Visual Object Tracking on Embedded Device.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018
2017
IEICE Electron. Express, 2017
Instruction set extension and hardware acceleration for SVM application toward a vector processor.
Proceedings of the International SoC Design Conference, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
Parallel implementations of SHA-3 on a 24-core processor with software and hardware co-design.
Proceedings of the 12th IEEE International Conference on ASIC, 2017
Fp<sup>2</sup> arithmetic acceleration based on modified Barrett modular multiplication algorithm.
Proceedings of the 12th IEEE International Conference on ASIC, 2017
A high utilization FPGA-based accelerator for variable-scale convolutional neural network.
Proceedings of the 12th IEEE International Conference on ASIC, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
Proceedings of the International SoC Design Conference, 2016
A low-cost and energy-efficient EEG processor for continuous seizure detection using wavelet transform and AdaBoost.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
2015
Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process.
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
An Energy-Efficient Design for ECG Recording and R-Peak Detection Based on Wavelet Transform.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
A Heterogeneous Multicore Crypto-Processor With Flexible Long-Word-Length Computation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
IEEE Signal Process. Lett., 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
Parallel implementation of AES on 2.5D multicore platform with hardware and software co-design.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
A lifting-based 2-D discrete wavelet transform architecture for data compression of bio-potential signals.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2014
An Efficient Implementation of Montgomery Multiplication on Multicore Platform With Optimized Algorithm, Task Partitioning, and Network Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing.
IEICE Electron. Express, 2014
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
An Ultra-Low Power QRS Complex Detection Algorithm Based on Down-Sampling Wavelet Transform.
IEEE Signal Process. Lett., 2013
Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65 nm CMOS.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
Robustness Analysis of Mesh-Based Network-on-Chip Architecture under Flooding-Based Denial of Service Attacks.
Proceedings of the IEEE Eighth International Conference on Networking, 2013
A 920MHz quad-core cryptography processor accelerating parallel task processing of public-key algorithms.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
A highly energy-efficient compressed sensing encoder with robust subthreshold clockless pipeline for wireless BANs.
Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013
An extensible and real-time compressive sensing reconstruction hardware for WBANs using OMP.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013
Design of a high throughput configurable variable-length FFT processor based on switch network architecture.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2013
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2013
2012
A High Speed Reconfigurable Face Detection Architecture Based on AdaBoost Cascade Algorithm.
IEICE Trans. Inf. Syst., 2012
Design Approach and Implementation of Application Specific Instruction Set Processor for SHA-3 BLAKE Algorithm.
IEICE Trans. Electron., 2012
IEICE Electron. Express, 2012
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2012
2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2010
Proceedings of the 2010 Wireless Telecommunications Symposium, 2010
Proceedings of the 2010 Wireless Telecommunications Symposium, 2010
2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
A full-custom design of AES SubByte module with signal independent power consumption.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
Two-dimensional Parity-based Concurrent Error Detection Method for AES Algorithm against Differential Fault Attack and its VLSI Implementation.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006