Design study of (2 x 2) core architecture for matrix multiplications via programmable graph architecture. - Jun-Hee Mun; Muling Peng; Sangjin Hong; Alex Doboli; K. Wendy Tang (SoCC, 2005)

Design and implementation of a high-speed matrix multiplier based on word-width decomposition. - Sangjin Hong; Kyoung-Su Park; Jun-Hee Mun (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Flexible Controller Design and Its Application for Concurrent Execution of Buffer Centric Dataflows. - Jun-Hee Mun; Shung Han Cho; Sangjin Hong (J. VLSI Signal Process., 2007)