On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture. - Jun Ho Bahn; Seung Eun Lee; Nader Bagherzadeh (ITNG, 2007)

Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP). - Seung Eun Lee; Jun Ho Bahn; Nader Bagherzadeh (SBAC-PAD, 2007)

Design of a router for network-on-chip. - Jun Ho Bahn; Seung Eun Lee; Nader Bagherzadeh (Int. J. High Perform. Syst. Archit., 2007)

A Generic Network Interface Architecture for a Networked Processor Array (NePA). - Seung Eun Lee; Jun Ho Bahn; Yoon Seok Yang; Nader Bagherzadeh (ARCS, 2008)

Efficient Parallel Buffer Structure and Its Management Scheme for a Robust Network-on-Chip (NoC) Architecture. - Jun Ho Bahn; Nader Bagherzadeh (CSICC, 2008)

Self-optimized Routing in a Network on-a-Chip. - Wolfgang Trumler; Sebastian Schlingmann; Theo Ungerer; Jun Ho Bahn; Nader Bagherzadeh (BICC, 2008)

Parallel FFT Algorithms on Network-on-Chips. - Jun Ho Bahn; Jungsook Yang; Nader Bagherzadeh (ITNG, 2008)

Design of simulation and analytical models for a 2D-meshed asymmetric adaptive router. - Jun Ho Bahn; Nader Bagherzadeh (IET Comput. Digit. Tech., 2008)

On Design and Application Mapping of a Network-on-Chip(NoC) Architecture. - Jun Ho Bahn; Seung Eun Lee; Yoon Seok Yang; Jungsook Yang; Nader Bagherzadeh (Parallel Process. Lett., 2008)

Parallel and Pipeline Processing for Block Cipher Algorithms on a Network-on-Chip. - Yoon Seok Yang; Jun Ho Bahn; Seung Eun Lee; Nader Bagherzadeh (ITNG, 2009)

Parallel LDPC Decoding on a Network-on-Chip Based Multiprocessor Platform. - Wen-Hsiang Hu; Jun Ho Bahn; Nader Bagherzadeh (SBAC-PAD, 2009)

Parallel FFT Algorithms on Network-on-Chips. - Jun Ho Bahn; Jungsook Yang; Wen-Hsiang Hu; Nader Bagherzadeh (J. Circuits Syst. Comput., 2009)

Parallel processing for block ciphers on a fault tolerant networked processor array. - Yoon Seok Yang; Jun Ho Bahn; Seung Eun Lee; Jungsook Yang; Nader Bagherzadeh (Int. J. High Perform. Syst. Archit., 2010)

Parallel low-density parity check decoding on a network-on-chip-based multiprocessor platform. - W.-H. Hu; C.-Y. Chen; Jun Ho Bahn; Nader Bagherzadeh (IET Comput. Digit. Tech., 2012)