A 10-b 320-MS/s Dual-Residue Pipelined SAR ADC with Binary Search Current Interpolator. - Kang-Il Cho; Yong-Sik Kwak; Ho-Jin Kim; Jun-Ho Boo; Seung-Hoon Lee 006; Gil-Cho Ahn (CICC, 2019)

A 101 dB Dynamic Range Delta-Sigma Modulator Using Modified Feed-Forward Architecture for Audio Application. - Jun-Young Kil; Kang-Il Cho; Ho-Jin Kim; Jun-Ho Boo; Yong-Sik Kwak; Gil-Cho Ahn (ISOCC, 2019)

A 10-b 900-MS/s Single-Channel Pipelined-SAR ADC Using Current-Mode Reference Scaling. - Kang-Il Cho; Ho-Jin Kim; Jun-Ho Boo; Yong-Sik Kwak; Jun-Sang Park; Seung-Hoon Lee 006; Gil-Cho Ahn (A-SSCC, 2020)

A 2.2mW 12-bit 200MS/s 28nm CMOS Pipelined SAR ADC with Dynamic Register-Based High-Speed SAR Logic. - Jun-Sang Park; Je-Min Jeon; Jun-Ho Boo; Jae-Hyuk Lee; Kang-Il Cho; Ho-Jin Kim; Gil-Cho Ahn; Seung-Hoon Lee 006 (A-SSCC, 2020)

A Third-Order DT Delta-Sigma Modulator With Noise-Coupling Technique. - Tae-Gwan Kim; Kang-Il Cho; Ho-Jin Kim; Jun-Ho Boo; Yong-Sik Kwak; Gil-Cho Ahn (ISOCC, 2020)

A 0.9V 0.022mm2 103dB DR Switched-Capacitor Audio Delta-Sigma Modulator Using Input-Referred kT/C Noise Reduction Technique. - Yong-Sik Kwak; Ho-Jin Kim; Kang-Il Cho; Jun-Ho Boo; Gil-Cho Ahn (A-SSCC, 2021)

A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3σ Inaccuracy of +0.02%, -0.12% for Battery-Monitoring Applications. - Jun-Ho Boo; Kang-Il Cho; Ho-Jin Kim; Jae-Geun Lim; Yong-Sik Kwak; Seung-Hoon Lee 006; Gil-Cho Ahn (IEEE J. Solid State Circuits, 2021)

A 96dB Dynamic Range 2kHz Bandwidth 2nd Order Delta-Sigma Modulator Using Modified Feed-Forward Architecture With Delayed Feedback. - Ju-Hye Han; Kang-Il Cho; Ho-Jin Kim; Jun-Ho Boo; Jae Sang Kim; Gil-Cho Ahn (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 430-MS/s 7-b Asynchronous SAR ADC With a 40 fF Input Sampling Capacitor. - Hyoung-Jung Kim; Jae-Hyuk Lee; Jae-Geun Lim; Jun-Ho Boo; Ho-Jin Kim; Seong-Bo Park; Youngdon Choi; Jung-Hwan Choi; Gil-Cho Ahn (ISOCC, 2022)

A 12-bit 3-MS/s Synchronous SAR ADC With a Hybrid RC DAC. - Mi-Ji Go; Jun-Ho Boo; Jae-Geun Lim; Hyoung-Jung Kim; Jae-Hyuk Lee; Seong-Bo Park; Byeongho Yu; Won-Jun Cho; Gil-Cho Ahn (ISOCC, 2023)

A Second-Order DT Delta-Sigma Modulator with Noise-Shaping SAR Quantizer. - Seong-Bo Park; Jun-Ho Boo; Jae-Geun Lim; Hyoung-Jung Kim; Jae-Hyuk Lee; Won-Jun Cho; Gil-Cho Ahn (ISOCC, 2023)

A Single-Loop Third-Order 10-MHz BW Source-Follower-Integrator Based Discrete-Time Delta-Sigma ADC. - Ho-Jin Kim; Jun-Ho Boo; Kang-Il Cho; Yong-Sik Kwak; Gil-Cho Ahn (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A CMOS Analog Front-End for Hall Sensor Readout IC. - Kang-Il Cho; Jun-Ho Boo; Jae-Geun Lim; Gil-Cho Ahn (ICEIC, 2024)

A Two-Step ADC with a Separate DAC Method for Enhanced Sub-Quantizer Settling Condition. - Jae-Geun Lim; Jun-Ho Boo; Hyoung-Jung Kim; Jae-Hyuk Lee; Kang-Il Cho; Gil-Cho Ahn (ICEIC, 2025)