A Digital CMOS PWCL With Fixed-Delay Rising Edge and Digital Stability Control. - Young-Chan Jang; Jun-Hyun Bae; Hong-June Park (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

An All-Digital 90-Degree Phase-Shift DLL with Loop-Embedded DCC for 1.6Gbps DDR Interface. - Jun-Hyun Bae; Jin-Ho Seo; Hwan-Seok Yeo; Jae-Whui Kim; Jae-Yoon Sim; Hong-June Park (CICC, 2007)

An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock Generator. - Young-Chan Jang; Jun-Hyun Bae; Sang-Hune Park; Jae-Yoon Sim; Hong-June Park (IEICE Trans. Electron., 2007)

A crosstalk-and-ISI equalizing receiver in 2-drop single-ended SSTL memory channel. - Jun-Hyun Bae; Young-Soo Sohn; Seung-Jun Bae; Kwang-Il Park; Joo-Sun Choi; Young-Hyun Jun; Jae-Yoon Sim; Hong-June Park (CICC, 2010)

A Digital Differential Transmitter with Pseudo-LVDS Output Driver and Digital Mismatch Calibration. - Jun-Hyun Bae; Sang-Hune Park; Jae-Yoon Sim; Hong-June Park (IEICE Trans. Electron., 2010)

Effective Fixed-Point Pipelined Divider for Mobile Rendering Processors. - Yong-Jin Park; Woo-Chan Park; Jun-Hyun Bae; Jin-Hong Park; Tack-Don Han (IEICE Trans. Inf. Syst., 2013)

A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMs. - Ji-Hoon Lim; Jun-Hyun Bae; Jaemin Jang; Hae-Kang Jung; Hyunbae Lee; Yongju Kim; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Meta-Learned Invariant Risk Minimization. - Jun-Hyun Bae; Inchul Choi; Minho Lee 001 (CoRR, 2021)

Learning Associative Reasoning Towards Systematicity Using Modular Networks. - Jun-Hyun Bae; Taewon Park; Minho Lee 001 (ICONIP (2), 2022)

Adaptive Bias Discovery for Learning Debiased Classifier. - Jun-Hyun Bae; Minho Lee 001; Heechul Jung (ACCV (8), 2024)

Invariant Risk Minimization in Medical Imaging with Modular Data Representation. - Jun-Hyun Bae; Chanwoo Kim; Tae-Young Chang (ICEIC, 2024)