An 8-ns 1-Mbit ECL BiCMOS SRAM with double-latch ECL-to-CMOS-level converters. - Masataka Matsui; Hiroshi Momose; Yukihiro Urakawa; Takeo Maeda; Azuma Suzuki; Nobuaki Urakawa; Katsuhiko Sato; Jun'ichi Matsunaga; Kiyofumi Ochii (IEEE J. Solid State Circuits, 1989)