First Prototype of a Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells. - Masahiro Koga; Masahiro Iida; Motoki Amagasaki; Yoshinobu Ichida; Mitsuro Saji; Jun Iida; Toshinori Sueyoshi (FPL, 2010)

A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells. - Masahiro Iida; Masahiro Koga; Kazuki Inoue; Motoki Amagasaki; Yoshinobu Ichida; Mitsuro Saji; Jun Iida; Toshinori Sueyoshi (IEICE Trans. Electron., 2011)

An Easily Testable Routing Architecture and Prototype Chip. - Kazuki Inoue; Masahiro Koga; Motoki Amagasaki; Masahiro Iida; Yoshinobu Ichida; Mitsuro Saji; Jun Iida; Toshinori Sueyoshi (IEICE Trans. Inf. Syst., 2012)