A modified two-step SOVA-based turbo decoder with a fixed scaling factor. - Dai Won Kim; Taek Won Kwon; Jun Rim Choi; Jun Jin Kong (ISCAS, 2000)

High-speed add-compare-select units using locally self-resetting CMOS. - Gunok Jung; Jun Jin Kong; Gerald E. Sobelman; Keshab K. Parhi (ISCAS (1), 2002)

Interleaved Convolutional Code and Its Viterbi Decoder Architecture. - Jun Jin Kong; Keshab K. Parhi (EURASIP J. Adv. Signal Process., 2003)

Low-latency architectures for high-throughput rate Viterbi decoders. - Jun Jin Kong; Keshab K. Parhi (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Error control coding and signal processing for flash memories. - Beomkyu Shin; Changkyu Seol; Jung-Soo Chung; Jun Jin Kong (ISCAS, 2012)

Verify level control criteria for multi-level cell flash memories and their applications. - Yongjune Kim 001; Jaehong Kim 008; Jun Jin Kong; B. V. K. Vijaya Kumar; Xin Li 001 (EURASIP J. Adv. Signal Process., 2012)

Modulation coding for flash memories. - Yongjune Kim 001; B. V. K. Vijaya Kumar; Kyoung Lae Cho; Hongrak Son; Jaehong Kim 008; Jun Jin Kong; Jaejin Lee (ICNC, 2013)

A post-processing algorithm for reducing strong error effects in NAND flash memory. - Sung-Rae Kim; Kijun Lee; Gyuyeol Kong; Myung-Kyu Lee; Dongmin Shin; Geunyeong Yu; Beomkyu Shin; Pilsang Yoon; Hongrak Son; Jun Jin Kong (APCCAS, 2016)

Efficient decoding of block turbo codes. - Jaeyong Son; Jun Jin Kong; Kyeongcheol Yang (J. Commun. Networks, 2018)

22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme. - Chi-Sung Oh; Ki Chul Chun; Young-Yong Byun; Yong-Ki Kim; So-Young Kim; Yesin Ryu; Jaewon Park; Sinho Kim; Sang-uhn Cha; Dong-Hak Shin; Jungyu Lee 002; Jong-Pil Son; et al. (ISSCC, 2020)

A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme. - Ki Chul Chun; Yong-Ki Kim; Yesin Ryu; Jaewon Park; Chi Sung Oh; Young-Yong Byun; So-Young Kim; Dong-Hak Shin; Jun Gyu Lee 002; Byung-Kyu Ho; Min-Sang Park; Seong-Jin Cho; et al. (IEEE J. Solid State Circuits, 2021)