3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS. - Takashi Kawamoto; Takayasu Norimatsu; Kenji Kogo; Fumio Yuki; Norio Nakajima; Masatoshi Tsuge; Tatsunori Usugi; Tomofumi Hokari; Hideki Koba; Takemasa Komori; Junya Nasu; Tsuneo Kawamata; et al. (ISSCC, 2015)