A linear fractional transform (LFT) based model for interconnect parametric uncertainty. - Janet Meiling Wang; Omar Hafiz; Jun Li 066 (DAC, 2004)

A Probabilistic Collocation Method Based Statistical Gate Delay Model Considering Process Variations and Multiple Input Switching. - Y. Satish Kumar; Jun Li 066; Claudio Talarico; Janet Meiling Wang (DATE, 2005)

System-level power and thermal modeling and analysis by orthogonal polynomial based response surface approach (OPRS). - Janet Meiling Wang; Bharat Srinivas; Dongsheng Ma; Charlie Chung-Ping Chen; Jun Li 066 (ICCAD, 2005)

Uncertainty modeling of gate delay considering multiple input switching. - Satish K. Yanamanamanda; Jun Li 066; Janet Meiling Wang (ISCAS (3), 2005)

Modeling the Driver Load in the Presence of Process Variations. - Janet Meiling Wang; Jun Li 066; Satish K. Yanamanamanda; Lakshmi Kalpana Vakati; Kishore Kumar Muchherla (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Chebyshev Affine Arithmetic based parametric yield prediction under limited descriptions of uncertainty. - Jin Sun 006; Yue Huang; Jun Li 066; Janet Meiling Wang (ASP-DAC, 2008)

Chebyshev Affine-Arithmetic-Based Parametric Yield Prediction Under Limited Descriptions of Uncertainty. - Jin Sun 006; Jun Li 066; Dongsheng Ma; Janet Meiling Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)