Low-complexity shift-LDPC decoder for high-speed communication systems. - Chuan Zhang 001; Li Li 003; Jun Lin 001; Zhongfeng Wang 001 (APCCAS, 2008)

LDPC Decoder Design for IEEE 802.15 Standard. - Jin Sha; Jun Lin 001; Li Li 003; Minglun Gao; Zhongfeng Wang 001 (ISCAS, 2009)

An improved min-sum based column-layered decoding algorithm for LDPC codes. - Jun Lin 001; Jin Sha; Zhongfeng Wang 001; Li Li 003 (SiPS, 2009)

Efficient Shuffle Network Architecture and Application for WiMAX LDPC Decoders. - Jun Lin 001; Zhongfeng Wang 001; Li Li 003; Jin Sha; Minglun Gao (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Decoder Design for RS-Based LDPC Codes. - Jin Sha; Jun Lin 001; Zhongfeng Wang 001; Li Li 003; Minglun Gao (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

LDPC decoder design for high rate wireless personal area networks. - Jin Sha; Jun Lin 001; Zhongfeng Wang 001; Li Li 003; Minglun Gao (IEEE Trans. Consumer Electron., 2009)

Efficient Decoder Design for Nonbinary Quasicyclic LDPC Codes. - Jun Lin 001; Jin Sha; Zhongfeng Wang 001; Li Li 003 (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

An Efficient VLSI Architecture for Nonbinary LDPC Decoders. - Jun Lin 001; Jin Sha; Zhongfeng Wang 001; Li Li 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Flexible LDPC Decoder Design for Multigigabit-per-Second Applications. - Chuan Zhang 001; Zhongfeng Wang 001; Jin Sha; Li Li 003; Jun Lin 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Modified shuffled schedule for nonbinary low-density parity-check codes. - Jun Lin 001; Zhiyuan Yan 001 (ISCAS, 2012)

Efficient Kötter-Kschischang Decoder Architectures for Noncoherent Error Control in Random Linear Network Coding. - Jun Lin 001; Hongmei Xie; Zhiyuan Yan 001 (SiPS, 2012)

Reduced-Complexity Decoders of Long Reed-Solomon Codes Based on Composite Cyclotomic Fourier Transforms. - Xuebin Wu; Zhiyuan Yan 001; Jun Lin 001 (IEEE Trans. Signal Process., 2012)

A decoding algorithm with reduced complexity for non-binary LDPC codes over large fields. - Jun Lin 001; Zhiyuan Yan 001 (ISCAS, 2013)

Linearized Polynomial Interpolation and Its Applications. - Hongmei Xie; Jun Lin 001; Zhiyuan Yan 001; Bruce W. Suter (IEEE Trans. Signal Process., 2013)

Efficient Shuffled Decoder Architecture for Nonbinary Quasi-Cyclic LDPC Codes. - Jun Lin 001; Zhiyuan Yan 001 (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Efficient list decoder architecture for polar codes. - Jun Lin 001; Zhiyuan Yan 001 (ISCAS, 2014)

A reduced latency list decoding algorithm for polar codes. - Jun Lin 001; Chenrong Xiong; Zhiyuan Yan 001 (SiPS, 2014)

Symbol-based successive cancellation list decoder for polar codes. - Chenrong Xiong; Jun Lin 001; Zhiyuan Yan 001 (SiPS, 2014)

An Efficient Fully Parallel Decoder Architecture for Nonbinary LDPC Codes. - Jun Lin 001; Zhiyuan Yan 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Efficient Error Control Decoder Architectures for Noncoherent Random Linear Network Coding. - Jun Lin 001; Hongmei Xie; Zhiyuan Yan 001 (J. Signal Process. Syst., 2014)

A hybrid partial sum computation unit architecture for list decoders of polar codes. - Jun Lin 001; Zhiyuan Yan 001 (ICASSP, 2015)

Reduced complexity belief propagation decoders for polar codes. - Jun Lin 001; Chenrong Xiong; Zhiyuan Yan 001 (SiPS, 2015)

Efficient approximate ML decoding units for polar list decoders. - Chenrong Xiong; Jun Lin 001; Zhiyuan Yan 001 (SiPS, 2015)

A multi-mode area-efficient SCL polar decoder. - Chenrong Xiong; Jun Lin 001; Zhiyuan Yan 001 (CoRR, 2015)

An Efficient List Decoder Architecture for Polar Codes. - Jun Lin 001; Zhiyuan Yan 001 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Error performance analysis of the symbol-decision SC polar decoder. - Chenrong Xiong; Jun Lin 001; Zhiyuan Yan 001 (ICASSP, 2016)

Accurate runtime thermal prediction scheme for 3D NoC systems with noisy thermal sensors. - Yuxiang Fu; Li Li 003; Hongbing Pan; Kun Wang 005; Feng Han 008; Jun Lin 001 (ISCAS, 2016)

A high throughput belief propagation decoder architecture for polar codes. - Jun Lin 001; Jin Sha; Li Li 003; Chenrong Xiong; Zhiyuan Yan 001; Zhongfeng Wang 001 (ISCAS, 2016)

Stage-combined belief propagation decoding of polar codes. - Jin Sha; Jun Lin 001; Zhongfeng Wang 001 (ISCAS, 2016)

An Efficient Hardware Architecture for Lossless Data Compression in Data Center. - Zhisheng Wang; Jun Lin 001; Zhongfeng Wang 001 (SiPS, 2016)

Intra-layer nonuniform quantization of convolutional neural network. - Fangxuan Sun; Jun Lin 001; Zhongfeng Wang 001 (WCSP, 2016)

Efficient convolution architectures for convolutional neural network. - Jichen Wang; Jun Lin 001; Zhongfeng Wang 001 (WCSP, 2016)

An ultra-long FFT architecture implemented in a reconfigurable application specified processor. - Feng Han 008; Li Li 003; Kun Wang 005; Fan Feng; Hongbing Pan; Baoning Zhang; Guoqiang He; Jun Lin 001 (IEICE Electron. Express, 2016)

Design and implementation of high performance matrix inversion based on reconfigurable processor. - Kun Wang 005; Li Li 003; Feng Han 008; Fan Feng; Jun Lin 001 (IEICE Electron. Express, 2016)

Symbol-Decision Successive Cancellation List Decoder for Polar Codes. - Chenrong Xiong; Jun Lin 001; Zhiyuan Yan 001 (IEEE Trans. Signal Process., 2016)

A High Throughput List Decoder Architecture for Polar Codes. - Jun Lin 001; Chenrong Xiong; Zhiyuan Yan 001 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A Multimode Area-Efficient SCL Polar Decoder. - Chenrong Xiong; Jun Lin 001; Zhiyuan Yan 001 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Energy efficient SVM classifier using approximate computing. - Yangcan Zhou; Jun Lin 001; Zhongfeng Wang 001 (ASICON, 2017)

Efficient approximate layered LDPC decoder. - Yangcan Zhou; Jun Lin 001; Zhongfeng Wang 001 (ISCAS, 2017)

Low-complexity detection algorithms based on matrix partition for massive MIMO. - Haijian Wu; Jun Lin 001; Chuan Zhang 001; Zhongfeng Wang 001 (WCSP, 2017)

Reduced complexity message passing detection algorithm in large-scale MIMO systems. - Haochuan Zhu; Jun Lin 001; Zhongfeng Wang 001 (WCSP, 2017)

An access pattern based adaptive mapping function for GPGPU scratchpad memory. - Feng Han 008; Li Li 003; Kun Wang 005; Fan Feng; Hongbing Pan; Jin Sha; Jun Lin 001 (IEICE Electron. Express, 2017)

Optimized sorting network for successive cancellation list decoding of polar codes. - Kun Wang 005; Li Li 003; Feng Han 008; Fan Feng; Jun Lin 001; Yuxiang Fu; Jin Sha (IEICE Electron. Express, 2017)

Efficient Soft Cancelation Decoder Architectures for Polar Codes. - Jun Lin 001; Zhiyuan Yan 001; Zhongfeng Wang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Accelerating Recurrent Neural Networks: A Memory-Efficient Approach. - Zhisheng Wang; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Efficient Reconfigurable Hardware Core for Convolutional Neural Networks. - Haonan Wang; Jun Lin 001; Yi Xie 001; Bo Yuan 001; Zhongfeng Wang 001 (ACSSC, 2018)

A Novel Compiler for Regular Expression Matching Engine Construction. - Xin Jin; Jun Lin 001; Zhongfeng Wang 001 (APCCAS, 2018)

Analysis of the Dual-Threshold-Based Shrinking Scheme for Efficient NB-LDPC Decoding. - Jing Tian 004; Jun Lin 001; Zhongfeng Wang 001 (APCCAS, 2018)

A High-Speed and Low-Complexity Architecture for Softmax Function in Deep Learning. - Meiqi Wang; Siyuan Lu 002; Danyang Zhu; Jun Lin 001; Zhongfeng Wang 001 (APCCAS, 2018)

Fast and Low-Complexity Decoding Algorithm and Architecture for Quadruple-Error-Correcting RS codes. - Zengchao Yan; Wenjie Li 003; Jun Lin 001; Zhongfeng Wang 001 (APCCAS, 2018)

Eadnet: Efficient Architecture for Decomposed Convolutional Neural Networks. - Fangxuan Sun; Jun Lin 001; Zhongfeng Wang 001 (ICASSP, 2018)

Approximate Belief Propagation Decoder for Polar Codes. - Menghui Xu; Shusen Jing; Jun Lin 001; Weikang Qian; Zaichen Zhang; Xiaohu You 001; Chuan Zhang 001 (ICASSP, 2018)

An Efficient NB-LDPC Decoding Algorithm for Next-Generation Memories. - Jing Tian 004; Jun Lin 001; Zhongfeng Wang 001 (ISCAS, 2018)

A New Soft-input Hard-output decoding algorithm for Turbo Product Codes. - Yaqi Wang; Jun Lin 001; Zhongfeng Wang 001 (ISCAS, 2018)

An Efficient Convolution Core Architecture for Privacy-Preserving Deep Learning. - Yizhi Wang; Jun Lin 001; Zhongfeng Wang 001 (ISCAS, 2018)

An Optimized Architecture For Decomposed Convolutional Neural Networks. - Fangxuan Sun; Jun Lin 001; Zhongfeng Wang 001 (ISVLSI, 2018)

FPAP: A Folded Architecture for Efficient Computing of Convolutional Neural Networks. - Yizhi Wang; Jun Lin 001; Zhongfeng Wang 001 (ISVLSI, 2018)

A Low-Complexity Massive MIMO Detection Algorithm Based on Matrix Partition. - Yahui Ji; Zhizhen Wu; Yifei Shen; Jun Lin 001; Zaichen Zhang; Xiaohu You 001; Chuan Zhang 001 (SiPS, 2018)

Bandwidth Efficient Architectures for Convolutional Neural Network. - Jichen Wang; Jun Lin 001; Zhongfeng Wang 001 (SiPS, 2018)

Approximate Comparator: Design and Analysis. - Yangcan Zhou; Jun Lin 001; Jichen Wang; Zhongfeng Wang 001 (SiPS, 2018)

SGAD: Soft-Guided Adaptively-Dropped Neural Network. - Zhisheng Wang; Fangxuan Sun; Jun Lin 001; Zhongfeng Wang 001; Bo Yuan 001 (CoRR, 2018)

Parameter-Free ℓp-Box Decoding of LDPC Codes. - Qiong Wu 005; Fan Zhang 060; Hao Wang 045; Jun Lin 001; Yang Liu 017 (IEEE Commun. Lett., 2018)

Hardware-Oriented Compression of Long Short-Term Memory for Efficient Inference. - Zhisheng Wang; Jun Lin 001; Zhongfeng Wang 001 (IEEE Signal Process. Lett., 2018)

A 21.66 Gbps Nonbinary LDPC Decoder for High-Speed Communications. - Jing Tian 004; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Efficient Hardware Architectures for Deep Convolutional Neural Network. - Jichen Wang; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

An Improved Gauss-Seidel Algorithm and Its Efficient Architecture for Massive MIMO Systems. - Jing Zeng; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

An Energy-Efficient Architecture for Binary Weight Convolutional Neural Networks. - Yizhi Wang; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A Stage-Combined Belief Propagation Decoder for Polar Codes. - Jin Sha; Jingbo Liu; Jun Lin 001; Zhongfeng Wang 001 (J. Signal Process. Syst., 2018)

Low Complexity Message Passing Detection Algorithm for Large-Scale MIMO Systems. - Jing Zeng; Jun Lin 001; Zhongfeng Wang 001 (IEEE Wirel. Commun. Lett., 2018)

An Enhanced Offset Min-Sum decoder for 5G LDPC Codes. - Hangxuan Cui; Khoa LeTrung; Fakhreddine Ghaffari; David Declercq; Jun Lin 001; Zhongfeng Wang 001 (APCC, 2019)

Redundancy-Aided Iterative Reliability-Based Majority-Logic Decoding for NB-LDPC Codes. - Suwen Song; Jing Tian 004; Jun Lin 001; Zhongfeng Wang 001 (ASICON, 2019)

A Low-latency Sparse-Winograd Accelerator for Convolutional Neural Networks. - Haonan Wang; Wenjian Liu; Tianyi Xu; Jun Lin 001; Zhongfeng Wang 001 (ICASSP, 2019)

A New Fast-SSC-Flip Decoding of Polar Codes. - Yangcan Zhou; Jun Lin 001; Zhongfeng Wang 001 (ICC, 2019)

TIE: energy-efficient tensor train-based inference engine for deep neural network. - Chunhua Deng; Fangxuan Sun; Xuehai Qian; Jun Lin 001; Zhongfeng Wang 001; Bo Yuan 001 (ISCA, 2019)

A New Probabilistic Gradient Descent Bit Flipping Decoder for LDPC Codes. - Hangxuan Cui; Jun Lin 001; Suwen Song; Zhongfeng Wang 001 (ISCAS, 2019)

USCA: A Unified Systolic Convolution Array Architecture for Accelerating Sparse Neural Network. - Wenjian Liu; Jun Lin 001; Zhongfeng Wang 001 (ISCAS, 2019)

Methodology for Efficient Reconfigurable Architecture of Generative Neural Network. - Wendong Mao; Jichen Wang; Jun Lin 001; Zhongfeng Wang 001 (ISCAS, 2019)

A Novel Low-Complexity Joint Coding and Decoding Algorithm for NB-LDPC Codes. - Suwen Song; Jing Tian 004; Jun Lin 001; Zhongfeng Wang 001 (ISCAS, 2019)

A Decomposition Mapping based Quantized Belief Propagation Decoding for 5G LDPC Codes. - Hangxuan Cui; Khoa Le; Fakhreddine Ghaffari; David Declercq; Jun Lin 001; Zhongfeng Wang 001 (ISCIT, 2019)

Fast-ABC: A Fast Architecture for Bottleneck-Like Based Convolutional Neural Networks. - Xiaoru Xie; Fangxuan Sun; Jun Lin 001; Zhongfeng Wang 001 (ISVLSI, 2019)

A Low-Complexity RS Decoder for Triple-Error-Correcting RS Codes. - Zengchao Yan; Jun Lin 001; Zhongfeng Wang 001 (ISVLSI, 2019)

Hardware Implementation of Improved Fast-SSC-Flip Decoder for Polar Codes. - Jing Zeng; Yangcan Zhou; Jun Lin 001; Zhongfeng Wang 001 (ISVLSI, 2019)

EAGLE: Exploiting Essential Address in Both Weight and Activation to Accelerate CNN Computing. - Wenjian Liu; Xiayuan Wen; Jun Lin 001; Zhongfeng Wang 001; Li Du (SiPS, 2019)

A Low-Latency and Low-Complexity Hardware Architecture for CTC Beam Search Decoding. - Siyuan Lu 002; Jinming Lu; Jun Lin 001; Zhongfeng Wang 001; Li Du (SiPS, 2019)

DynExit: A Dynamic Early-Exit Strategy for Deep Residual Networks. - Meiqi Wang; Jianqiao Mo; Jun Lin 001; Zhongfeng Wang 001; Li Du (SiPS, 2019)

A Low-Complexity Error-and-Erasure Decoding Algorithm for t=2 RS Codes. - Zengchao Yan; Wenjie Li 003; Jun Lin 001; Zhongfeng Wang 001 (SiPS, 2019)

Hybrid Preconditioned CG Detection with Sequential Update for Massive MIMO Systems. - Jing Zeng; Jun Lin 001; Zhongfeng Wang 001; Yun Chen 001 (SiPS, 2019)

Training Deep Neural Networks Using Posit Number System. - Jinming Lu; Siyuan Lu 002; Zhisheng Wang; Chao Fang; Jun Lin 001; Zhongfeng Wang 001; Li Du (SoCC, 2019)

A Hardware-Oriented and Memory-Efficient Method for CTC Decoding. - Siyuan Lu 002; Jinming Lu; Jun Lin 001; Zhongfeng Wang 001 (IEEE Access, 2019)

Efficient T-EMS Based Decoding Algorithms for High-Order LDPC Codes. - Jing Tian 004; Suwen Song; Jun Lin 001; Zhongfeng Wang 001 (IEEE Access, 2019)

Design Light-weight 3D Convolutional Networks for Video Recognition Temporal Residual, Fully Separable Block, and Fast Algorithm. - Haonan Wang; Jun Lin 001; Zhongfeng Wang 001 (CoRR, 2019)

E-LSTM: An Efficient Hardware Architecture for Long Short-Term Memory. - Meiqi Wang; Zhisheng Wang; Jinming Lu; Jun Lin 001; Zhongfeng Wang 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2019)

High-Speed Modular Multipliers for Isogeny-Based Post-Quantum Cryptography. - Jing Tian 004; Zhe Liu 001; Jun Lin 001; Zhongfeng Wang 001; Binjing Li (IACR Cryptol. ePrint Arch., 2019)

Modified GII-BCH Codes for Low-Complexity and Low-Latency Encoders. - Wenjie Li 003; Jing Tian 004; Jun Lin 001; Zhongfeng Wang 001 (IEEE Commun. Lett., 2019)

Improved Fast-SSC-Flip Decoding of Polar Codes. - Yangcan Zhou; Jun Lin 001; Zhongfeng Wang 001 (IEEE Commun. Lett., 2019)

An Efficient Post-Processor for Lowering the Error Floor of LDPC Codes. - Hangxuan Cui; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

An Improved Gradient Descent Bit-Flipping Decoder for LDPC Codes. - Hangxuan Cui; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 124-Gb/s Decoder for Generalized Integrated Interleaved Codes. - Wenjie Li 003; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

FPAP: A Folded Architecture for Energy-Quality Scalable Convolutional Neural Networks. - Yizhi Wang; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A High-Speed Successive-Cancellation Decoder for Polar Codes Using Approximate Computing. - Yangcan Zhou; Zhiyu Chen 003; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A New Clock Phase Calibration Method in High-Speed and High-Resolution DACs. - Congyi Zhu; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Background Calibration of Comparator Offsets in SHA-Less Pipelined ADCs. - Congyi Zhu; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Analysis and Design of a Large Dither Injection Circuit for Improving Linearity in Pipelined ADCs. - Congyi Zhu; Renrong Liang; Jun Lin 001; Zhongfeng Wang 001; Li Li 003 (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Efficient FPGA design for Convolutions in CNN based on FFT-pruning. - Liulu He; Xiaoru Xie; Jun Lin 001; Zhongfeng Wang 001 (APCCAS, 2020)

LBFP: Logarithmic Block Floating Point Arithmetic for Deep Neural Networks. - Chao Ni 005; Jinming Lu; Jun Lin 001; Zhongfeng Wang 001 (APCCAS, 2020)

In-Memory Computing: The Next-Generation AI Computing Paradigm. - Yufei Ma 002; Yuan Du; Li Du; Jun Lin 001; Zhongfeng Wang 001 (ACM Great Lakes Symposium on VLSI, 2020)

LSTM-Based Quantitative Trading Using Dynamic K-Top and Kelly Criterion. - Binjing Li; Keli Xie; Siyuan Lu 002; Jun Lin 001; Zhongfeng Wang 001 (IJCNN, 2020)

Hardware Accelerator for Engle-Granger Cointegration in Pairs Trading. - Shuang Liang 006; Siyuan Lu 002; Jun Lin 001; Zhongfeng Wang 001 (ISCAS, 2020)

A Three-Level Scoring System for Fast Similarity Evaluation Based on Smith-Waterman Algorithm. - Yujie Zhang; Jiajun Wu 004; Minghao Li 001; Jun Lin 001; Zhongfeng Wang 001 (ISCAS, 2020)

Exploring Quantization in Few-Shot Learning. - Meiqi Wang; Ruixin Xue; Jun Lin 001; Zhongfeng Wang 001 (NEWCAS, 2020)

A Computation-Efficient Solution for Acceleration of Generative Adversarial Network. - Peixiang Yang; Wendong Mao; Jun Lin 001; Zhongfeng Wang 001 (NEWCAS, 2020)

A Serial Maximum-likelihood Detection Algorithm for Massive MIMO Systems. - Jing Zeng; Jun Lin 001; Zhongfeng Wang 001 (NEWCAS, 2020)

Financial Time Series Forecasting Model Based on EMD and Rolling Grey Model. - Binjing Li; Fenggui Liu; Jun Lin 001; Zhongfeng Wang 001 (SiPS, 2020)

A Reconfigurable DNN Training Accelerator on FPGA. - Jinming Lu; Jun Lin 001; Zhongfeng Wang 001 (SiPS, 2020)

Temporal Residual Feature Learning for Efficient 3D Convolutional Neural Network on Action Recognition Task. - Haonan Wang; Yuchen Mei; Jun Lin 001; Zhongfeng Wang 001 (SiPS, 2020)

A Configurable FPGA Accelerator of Bi-LSTM Inference with Structured Sparsity. - Shouliang Guo; Chao Fang; Jun Lin 001; Zhongfeng Wang 001 (SoCC, 2020)

Hardware Accelerator for Multi-Head Attention and Position-Wise Feed-Forward in the Transformer. - Siyuan Lu 002; Meiqi Wang; Shuang Liang 006; Jun Lin 001; Zhongfeng Wang 001 (SoCC, 2020)

Ultra-Fast Modular Multiplication Implementation for Isogeny-Based Post-Quantum Cryptography. - Jing Tian 004; Jun Lin 001; Zhongfeng Wang 001 (IACR Cryptol. ePrint Arch., 2020)

Faster Software Implementation of the SIKE Protocol Based on A New Data Representation. - Jing Tian 004; Piaoyang Wang; Zhe Liu 001; Jun Lin 001; Zhongfeng Wang 001; Johann Großschädl (IACR Cryptol. ePrint Arch., 2020)

Multi-Layer Generalized Integrated Interleaved Codes. - Wenjie Li 003; Jun Lin 001; Zhongfeng Wang 001 (IEEE Commun. Lett., 2020)

A lightweight face detector by integrating the convolutional neural network with the image pyramid. - Jiapeng Luo; Jiaying Liu 001; Jun Lin 001; Zhongfeng Wang 001 (Pattern Recognit. Lett., 2020)

Fine-Grained Bit-Flipping Decoding for LDPC Codes. - Yuxing Chen; Hangxuan Cui; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A Precision-Scalable Energy-Efficient Convolutional Neural Network Accelerator. - Wenjian Liu; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst., 2020)

A Novel Iterative Reliability-Based Majority-Logic Decoder for NB-LDPC Codes. - Suwen Song; Hangxuan Cui; Jing Tian 004; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Optimized Trellis-Based Min-Max Decoder for NB-LDPC Codes. - Jing Tian 004; Suwen Song; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Efficient Precision-Adjustable Architecture for Softmax Function in Deep Learning. - Danyang Zhu; Siyuan Lu 002; Meiqi Wang; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst., 2020)

Information Storage Bit-Flipping Decoder for LDPC Codes. - Hangxuan Cui; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2020)

F-DNA: Fast Convolution Architecture for Deconvolutional Network Acceleration. - Wendong Mao; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Counter Random Gradient Descent Bit-Flipping Decoder for LDPC Codes. - Keyue Deng; Hangxuan Cui; Jun Lin 001; Zhongfeng Wang 001 (ISVLSI, 2021)

PipeBSW: A Two-Stage Pipeline Structure for Banded Smith-Waterman Algorithm on FPGA. - Luyi Li; Jun Lin 001; Zhongfeng Wang 001 (ISVLSI, 2021)

An FPGA-Based Reconfigurable Accelerator for Low-Bit DNN Training. - Haikuo Shao; Jinming Lu; Jun Lin 001; Zhongfeng Wang 001 (ISVLSI, 2021)

Automatic Generation of Dynamic Inference Architecture for Deep Neural Networks. - Shize Zhao; Liulu He; Xiaoru Xie; Jun Lin 001; Zhongfeng Wang 001 (SiPS, 2021)

An Improved Reliability-Based Decoding Algorithm for NB-LDPC Codes. - Suwen Song; Jing Tian 004; Jun Lin 001; Zhongfeng Wang 001 (IEEE Commun. Lett., 2021)

Evaluations on Deep Neural Networks Training Using Posit Number System. - Jinming Lu; Chao Fang; Mingyang Xu; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Computers, 2021)

Design of High-Performance and Area-Efficient Decoder for 5G LDPC Codes. - Hangxuan Cui; Fakhreddine Ghaffari; Khoa Le; David Declercq; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Low-Latency Hardware Accelerator for Improved Engle-Granger Cointegration in Pairs Trading. - Shuang Liang 006; Siyuan Lu 002; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

An Efficient and Flexible Accelerator Design for Sparse Convolutional Neural Networks. - Xiaoru Xie; Jun Lin 001; Zhongfeng Wang 001; Jinghe Wei (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Fast Modular Multipliers for Supersingular Isogeny-Based Post-Quantum Cryptography. - Jing Tian 004; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2021)

An Efficient CNN Training Accelerator Leveraging Transposable Block Sparsity. - Mingyang Xu; Jinming Lu; Zhongfeng Wang 001; Jun Lin 001 (AICAS, 2022)

Magical-Decomposition: Winning Both Adversarial Robustness and Efficiency on Hardware. - Xin Cheng; Meiqi Wang; Yu-Bo Shi; Jun Lin 001; Zhongfeng Wang 001 (ICMLC, 2022)

An Efficient Hardware Accelerator for Sparse Transformer Neural Networks. - Chao Fang; Shouliang Guo; Wei Wu; Jun Lin 001; Zhongfeng Wang 001; Ming Kai Hsu; Lingzhi Liu (ISCAS, 2022)

Accelerate Three-Dimensional Generative Adversarial Networks Using Fast Algorithm. - Ziqi Su; Wendong Mao; Zhongfeng Wang 001; Jun Lin 001; Wenqiang Wang; Haitao Sun (ISCAS, 2022)

A Reconfigurable Approach for Deconvolutional Network Acceleration with Fast Algorithm. - Peixiang Yang; Wendong Mao; Zhongfeng Wang 001; Jun Lin 001 (ISCAS, 2022)

An Efficient FPGA Accelerator for Point Cloud. - Zilun Wang; Wendong Mao; Peixiang Yang; Zhongfeng Wang 001; Jun Lin 001 (SOCC, 2022)

Forecasting Stock Indexes with Metabolic DWT and MWA-GM(1,1). - Ziyang Jiang; Siyuan Lu 002; Jun Lin 001; Zhongfeng Wang 001 (WCSP, 2022)

Fast and Accurate FSA System Using ELBERT: An Efficient and Lightweight BERT. - Siyuan Lu 002; Chenchen Zhou; Keli Xie; Shiyi Liu; Jun Lin 001; Zhongfeng Wang 001 (CoRR, 2022)

Efficient Software Implementation of the SIKE Protocol Using a New Data Representation. - Jing Tian 004; Piaoyang Wang; Zhe Liu 001; Jun Lin 001; Zhongfeng Wang 001; Johann Großschädl (IEEE Trans. Computers, 2022)

A Proximal Iteratively Reweighted Approach for Efficient Network Sparsification. - Hao Wang 045; Xiangyu Yang; Yuanming Shi; Jun Lin 001 (IEEE Trans. Computers, 2022)

Rethinking Adaptive Computing: Building a Unified Model Complexity-Reduction Framework With Adversarial Robustness. - Meiqi Wang; Liulu He; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Neural Networks Learn. Syst., 2022)

An FPGA-Based Reconfigurable CNN Training Accelerator Using Decomposable Winograd. - Hui Wang 083; Jinming Lu; Jun Lin 001; Zhongfeng Wang 001 (ISVLSI, 2023)

Fast and Accurate FSA System Using ELBERT: An Efficient and Lightweight BERT. - Siyuan Lu 002; Chenchen Zhou; Keli Xie; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Signal Process., 2023)

An Efficient Massive MIMO Detector Based on Approximate Expectation Propagation. - Yangyang Chen 005; Suwen Song; Zhongfeng Wang 001; Jun Lin 001 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A Precision-Scalable RISC-V DNN Processor with On-Device Learning Capability at the Extreme Edge. - Longwei Huang; Chao Fang; Qiong Li; Jun Lin 001; Zhongfeng Wang 001 (ASPDAC, 2024)

A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference. - Chuanning Wang; Chao Fang; Xiao Wu; Zhongfeng Wang 001; Jun Lin 001 (ISCAS, 2024)

An FPGA-Based Accelerator Enabling Efficient Support for CNNs with Arbitrary Kernel Sizes. - Miaoxin Wang; Xiao Wu; Jun Lin 001; Zhongfeng Wang 001 (ISCAS, 2024)

SPEED: A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference. - Chuanning Wang; Chao Fang; Xiao Wu; Zhongfeng Wang 001; Jun Lin 001 (CoRR, 2024)

WinTA: An Efficient Reconfigurable CNN Training Accelerator With Decomposition Winograd. - Jinming Lu; Hui Wang 083; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Amoeba: An Efficient and Flexible FPGA-Based Accelerator for Arbitrary-Kernel CNNs. - Xiao Wu; Miaoxin Wang; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2024)

TECO: A Unified Feature Map Compression Framework Based on Transform and Entropy. - Yubo Shi; Meiqi Wang; Tianyu Cao; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Neural Networks Learn. Syst., 2024)

A High-Speed 8-bit Single-Channel SAR ADC with Tailored Bit Intervals. - Xinyu Li; Ruida Wang; Mengying Zhang; Congyi Zhu; Zhongfeng Wang 001; Jun Lin 001 (ISCAS, 2025)

SPEED: A Scalable RISC-V Vector Processor Enabling Efficient Multiprecision DNN Inference. - Chuanning Wang; Chao Fang; Xiao Wu; Zhongfeng Wang 001; Jun Lin 001 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Enable Lightweight and Precision-Scalable Posit/IEEE-754 Arithmetic in RISC-V Cores for Transprecision Computing. - Qiong Li; Chao Fang; Longwei Huang; Jun Lin 001; Zhongfeng Wang 001 (CoRR, 2025)

A RISC-V Domain-Specific Processor for Deep Learning-Based Channel Estimation. - Meng Guo; Qi Wu; Chuanning Wang; Yangcan Zhou; Shaowei Wang 001; Chuan Zhang 001; Zhongfeng Wang 001; Jun Lin 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)