Jun Ma

Affiliations:
  • Shanghai Jiao Tong University, School of Microelectronics, Shanghai, China


According to our database1, Jun Ma authored at least 13 papers between 2011 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Links

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Bibliography

2015
True-Damage-Aware Enumerative Coding for Improving nand Flash Memory Endurance.
IEEE Trans. Very Large Scale Integr. Syst., 2015

How Much Can Data Compressibility Help to Improve NAND Flash Memory Lifetime?
Proceedings of the 13th USENIX Conference on File and Storage Technologies, 2015

2014
Overclocking nand Flash Memory I/O Link in LDPC-Based SSDs.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

Realizing Unequal Error Correction for nand Flash Memory at Minimal Read Latency Overhead.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

2013
VLSI Implementation of a High-Throughput Iterative Fixed-Complexity Sphere Decoder.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

A memory efficient parallel layered QC-LDPC decoder for CMMB systems.
Integr., 2013

A soft-output parallel stack algorithm for MIMO detection.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

2012
High-throughput sorted MMSE QR decomposition for MIMO detection.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

VLSI implementation of an 855 Mbps high performance soft-output K-Best MIMO detector.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Parallel SFSD MIMO detection with SOFT-HARD combination enumeration.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

Generalized interleaving network based on configurable QPP architecture for parallel turbo decoder.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

Effective multi-standard macroblock prediction VLSI design for reconfigurable multimedia systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Memory efficient layered decoder design with early termination for LDPC codes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011


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