Physically Tightly Coupled, Logically Loosely Coupled, Near-Memory BNN Accelerator (PTLL-BNN). - Yun-Chen Lo; Yu-Chun Kuo; Yun-Sheng Chang; Jian-Hao Huang; Jun-Shen Wu; Wen-Chien Ting; Tai-Hsing Wen; Ren-Shuo Liu (ESSCIRC, 2019)

5.9 A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel. - Tzu-Hsiang Hsu; Yen-Kai Chen; Jun-Shen Wu; Wen-Chien Ting; Cheng-Te Wang; Chen-Fu Yeh; Syuan-Hao Sie; Yi-Ren Chen; Ren-Shuo Liu; Chung-Chuan Lo; Kea-Tiong Tang; Meng-Fan Chang; et al. (ISSCC, 2020)

Value-Aware Error Detection and Correction for SRAM Buffers in Low-Bitwidth, Floating-Point CNN Accelerators. - Jun-Shen Wu; Chi-En Wang; Ren-Shuo Liu (ASP-DAC, 2021)

ISSA: Input-Skippable, Set-Associative Computing-in-Memory (SA-CIM) Architecture for Neural Network Accelerators. - Yun-Chen Lo; Chih-Chen Yeh; Jun-Shen Wu; Chia-Chun Wang; Yu-Chih Tsai; Wen-Chien Ting; Ren-Shuo Liu (ICCAD, 2022)

Exploiting and Enhancing Computation Latency Variability for High-Performance Time-Domain Computing-in-Memory Neural Network Accelerators. - Chia-Chun Wang; Yun-Chen Lo; Jun-Shen Wu; Yu-Chih Tsai; Chia-Cheng Chang; Tsen-Wei Hsu; Min-Wei Chu; Chuan-Yao Lai; Ren-Shuo Liu (ICCD, 2023)

FM-P2L: An Algorithm Hardware Co-design of Fixed-Point MSBs with Power-of-2 LSBs in CNN Accelerators. - Jun-Shen Wu; Ren-Shuo Liu (ICCD, 2023)

SG-Float: Achieving Memory Access and Computing Power Reduction Using Self-Gating Float in CNNs. - Jun-Shen Wu; Tsen-Wei Hsu; Ren-Shuo Liu (ACM Trans. Embed. Comput. Syst., 2023)

ISSA: Architecting CNN Accelerators Using Input-Skippable, Set-Associative Computing-in-Memory. - Yun-Chen Lo; Jun-Shen Wu; Chia-Chun Wang; Yu-Chih Tsai; Chih-Chen Yeh; Wen-Chien Ting; Ren-Shuo Liu (IEEE Trans. Computers, 2024)