A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications. - Weng-Geng Ho; Ne Kyaw Zwa Lwin; Nay Aung Kyaw; Jun-Sheng Ng; Juncheng Chen; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2020)

A Highly Efficient Power Model for Correlation Power Analysis (CPA) of Pipelined Advanced Encryption Standard (AES). - Jun-Sheng Ng; Juncheng Chen; Nay Aung Kyaw; Ne Kyaw Zwa Lwin; Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee (ISCAS, 2020)

Normalized Differential Power Analysis - for Ghost Peaks Mitigation. - Juncheng Chen; Jun-Sheng Ng; Nay Aung Kyaw; Ne Kyaw Zwa Lwin; Weng-Geng Ho; Kwen-Siong Chong; Zhiping Lin 001; Joseph Sylvester Chang; Bah-Hwee Gwee (ISCAS, 2021)

Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation. - Kwen-Siong Chong; Jun-Sheng Ng; Juncheng Chen; Ne Kyaw Zwa Lwin; Nay Aung Kyaw; Weng-Geng Ho; Joseph Sylvester Chang; Bah-Hwee Gwee (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

A Novel Normalized Variance-Based Differential Power Analysis Against Masking Countermeasures. - Juncheng Chen; Jun-Sheng Ng; Kwen-Siong Chong; Zhiping Lin 001; Bah-Hwee Gwee (IEEE Trans. Inf. Forensics Secur., 2021)

Incremental Linear Regression Attack. - Juncheng Chen; Jun-Sheng Ng; Nay Aung Kyaw; Zhili Zou; Kwen-Siong Chong; Zhiping Lin 001; Bah-Hwee Gwee (AsianHOST, 2022)

Non-profiling based Correlation Optimization Deep Learning Analysis. - Juncheng Chen; Jun-Sheng Ng; Nay Aung Kyaw; Ne Kyaw Zwa Lwin; Kwen-Siong Chong; Zhiping Lin 001; Joseph Sylvester Chang; Bah-Hwee Gwee (ISCAS, 2022)

An Asynchronous-Logic Masked Advanced Encryption Standard (AES) Accelerator and its Side-Channel Attack Evaluations. - Jun-Sheng Ng; Juncheng Chen; Nay Aung Kyaw; Ne Kyaw Zwa Lwin; Kwen-Siong Chong; Joseph S. Chang; Bah-Hwee Gwee (ISCAS, 2022)

A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks. - Jun-Sheng Ng; Juncheng Chen; Kwen-Siong Chong; Joseph S. Chang; Bah-Hwee Gwee (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Improving FPGA-based Async-logic AES Accelerator with the Integration of Sync-logic Block RAMs. - Jun-Sheng Ng; Juncheng Chen; Si Wu; Nay Aung Kyaw; Kwen-Siong Chong; Zhiping Lin 001; Bah-Hwee Gwee (ISCAS, 2023)

An Energy-Efficient and High-Accuracy Spiking Neural Network Utilizing Asynchronous CORDIC for On-FPGA STDP Learning. - Shirui Sheng; Kwen-Siong Chong; Jun-Sheng Ng; Zhiping Lin 001; Joseph S. Chang; Bah-Hwee Gwee (APCCAS, 2024)

Securing Against Side-Channel Attacks With Wide-Range In Situ Random Voltage Dithering on Async-Logic AES Engine. - Jun-Sheng Ng; Juncheng Chen; Nay Aung Kyaw; Kwen-Siong Chong; Bah-Hwee Gwee (IEEE Trans. Very Large Scale Integr. Syst., 2024)