Microarchitectural-level statistical timing models for near-threshold circuit design. - Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (ASP-DAC, 2015)

An energy-efficient on-chip memory structure for variability-aware near-threshold operation. - Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (ISQED, 2015)

Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization. - Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring. - Islam A. K. M. Mahfuzul; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (IEEE J. Solid State Circuits, 2015)

A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region. - Tatsuya Kamakari; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (ASP-DAC, 2016)

Variability- and correlation-aware logical effort for near-threshold circuit design. - Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (ISQED, 2016)

Fully digital on-chip memory using minimum height standard cells for near-threshold voltage computing. - Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (PATMOS, 2016)

Analytical Stability Modeling for CMOS Latches in Low Voltage Operation. - Tatsuya Kamakari; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Pin accessibility evaluating model for improving routability of VLSI designs. - Hong-Yan Su; Shinichi Nishizawa; Yan-Shiun Wu; Jun Shiomi; Yih-Lang Li; Hidetoshi Onodera (SoCC, 2017)

A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation. - Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Performance Modeling and On-Chip Memory Structures for Minimum Energy Operation in Voltage-Scaled LSI Circuits. - Jun Shiomi (2017)

An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms Towards Light Speed Data Processing. - Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera; Akihiko Shinya; Masaya Notomi (ICRC, 2018)

Maximizing Energy Efficiency of on-Chip Caches Exploiting Hybrid Memory Structure. - Hongjie Xu; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (PATMOS, 2018)

Minimum Energy Point Tracking with All-Digital On-Chip Sensors. - Jun Shiomi; Shu Hokimoto; Tohru Ishihara; Hidetoshi Onodera (J. Low Power Electron., 2018)

BDD-based synthesis of optical logic circuits exploiting wavelength division multiplexing. - Ryosuke Matsuo; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera; Akihiko Shinya; Masaya Notomi (ASP-DAC, 2019)

An Optical Neural Network Architecture based on Highly Parallelized WDM-Multiplier-Accumulator. - Tohru Ishihara; Jun Shiomi; Naoki Hattori; Yutaka Masuda; Akihiko Shinya; Masaya Notomi (PHOTONICS@SC, 2019)

A Design Method of a Cell-Based Amplifier for Body Bias Generation. - Takuya Koyanagi; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (IEICE Trans. Electron., 2019)

Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits. - Ryosuke Matsuo; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera; Akihiko Shinya; Masaya Notomi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing. - Hongjie Xu; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

Area-efficient fully digital memory using minimum height standard cells for near-threshold voltage computing. - Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (Integr., 2019)

A DLL-based Body Bias Generator for Minimum Energy Operation with Independent P-well and N-well Bias. - Kentaro Nagai; Jun Shiomi; Hidetoshi Onodera (APCCAS, 2020)

On-chip Memory Optimized CNN Accelerator with Efficient Partial-sum Accumulation. - Hongjie Xu; Jun Shiomi; Hidetoshi Onodera (ACM Great Lakes Symposium on VLSI, 2020)

An Optical Accelerator for Deep Neural Network Based on Integrated Nanophotonics. - Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera; Akihiko Shinya; Masaya Notomi (ICRC, 2020)

Real-Time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy. - Khyati Kiyawat; Yutaka Masuda; Jun Shiomi; Tohru Ishihara (ISVLSI, 2020)

A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing. - Ryosuke Matsuo; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera; Akihiko Shinya; Masaya Notomi (ISVLSI, 2020)

Dynamic Supply and Threshold Voltage Scaling towards Runtime Energy Optimization over a Wide Operating Performance Region. - Shoya Sonoda; Jun Shiomi; Hidetoshi Onodera (SoCC, 2020)

Tamper-Resistant Optical Logic Circuits Based on Integrated Nanophotonics. - Jun Shiomi; Shuya Kotsugi; Boyu Dong; Hidetoshi Onodera; Akihiko Shinya; Masaya Notomi (DAC, 2021)

Integration of Minimum Energy Point Tracking and Soft Real-Time Scheduling for Edge Computing. - Takumi Komori; Yutaka Masuda; Jun Shiomi; Tohru Ishihara (ISQED, 2021)

Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation. - Naoki Hattori; Jun Shiomi; Yutaka Masuda; Tohru Ishihara; Akihiko Shinya; Masaya Notomi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021)

A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits. - Ryosuke Matsuo; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera; Akihiko Shinya; Masaya Notomi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021)

Supply and Threshold Voltage Scaling for Minimum Energy Operation over a Wide Operating Performance Region. - Shoya Sonoda; Jun Shiomi; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021)

Evaluation Metrics for the Cost of Data Movement in Deep Neural Network Acceleration. - Hongjie Xu; Jun Shiomi; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021)

A DLL-Based Body Bias Generator with Independent P-Well and N-Well Biasing for Minimum Energy Operation. - Kentaro Nagai; Jun Shiomi; Hidetoshi Onodera (IEICE Trans. Electron., 2021)

MOSDA: On-Chip Memory Optimized Sparse Deep Neural Network Accelerator With Efficient Index Matching. - Hongjie Xu; Jun Shiomi; Hidetoshi Onodera (IEEE Open J. Circuits Syst., 2021)

DistriHD: A Memory Efficient Distributed Binary Hyperdimensional Computing Architecture for Image Classification. - Dehua Liang; Jun Shiomi; Noriyuki Miura; Hiromitsu Awano (ASP-DAC, 2022)

Zero-standby-power Nonvolatile Standard Cell Memory Using FiCC for IoT Processors with Intermittent Operations. - Yuki Abe; Kazutoshi Kobayashi; Jun Shiomi; Hiroyuki Ochi (COOL CHIPS, 2022)

Approximation-Based Implementation for a Minimum Energy Point Tracking Algorithm over a Wide Operating Performance Region. - Shoya Sonoda; Jun Shiomi; Hidetoshi Onodera (LASCAS, 2022)

Real-time adaptive data filtering with multiple sensors for indoor monitoring. - Kuon Akiyama; Ryoichi Shinkuma; Jun Shiomi (NOMS, 2022)

Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits. - Jun Shiomi; Shogo Terada; Tohru Ishihara; Hidetoshi Onodera (SOCC, 2022)

Approximate Minimum Energy Point Tracking and Task Scheduling for Energy-Efficient Real-Time Computing. - Takumi Komori; Yutaka Masuda; Jun Shiomi; Tohru Ishihara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022)

A Hardware Efficient Reservoir Computing System Using Cellular Automata and Ensemble Bloom Filter. - Dehua Liang; Jun Shiomi; Noriyuki Miura; Masanori Hashimoto; Hiromitsu Awano (IEICE Trans. Inf. Syst., 2022)

DependableHD: A Hyperdimensional Learning Framework for Edge-Oriented Voltage-Scaled Circuits. - Dehua Liang; Hiromitsu Awano; Noriyuki Miura; Jun Shiomi (ASP-DAC, 2023)

A Triturated Sensing System. - Noriyuki Miura; Kotaro Naruse; Jun Shiomi; Yoshihiro Midoh; Tetsuya Hirose; Takaaki Okidono; Takuji Miki; Makoto Nagata (ISSCC, 2023)

A Self-Programming PUF Harvesting the High-Energy Plasma During Fabrication. - Kotaro Naruse; Takayuki Ueda; Jun Shiomi; Yoshihiro Midoh; Noriyuki Miura (ISSCC, 2023)

Approximation-Based System Implementation for Real-Time Minimum Energy Point Tracking over a Wide Operating Performance Region. - Shoya Sonoda; Jun Shiomi; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2023)

Nonvolatile Storage Cells Using FiCC for IoT Processors with Intermittent Operations. - Yuki Abe; Kazutoshi Kobayashi; Jun Shiomi; Hiroyuki Ochi (IEICE Trans. Electron., 2023)

Modeling of Tamper Resistance to Electromagnetic Side-channel Attacks on Voltage-scaled Circuits. - Kazuki Minamiguchi; Yoshihiro Midoh; Noriyuki Miura; Jun Shiomi (ASPDAC, 2024)

Edge-Oriented Point Cloud Compression by Moving Object Detection for Realtime Smart Monitoring. - Itsuki Takada; Daiki Nitto; Yoshihiro Midoh; Noriyuki Miura; Jun Shiomi; Ryoichi Shinkuma (CCNC, 2024)

Square-Wave Defined Pulse Generator for High Fidelity Gate Operation of Superconducting Qubits. - Ryosuke Matsuo; Kazuhisa Ogawa; Hidehisa Shiorni; Makoto Negoro; Ryutaco Ohira; Takefumi Miyoshi; Michihiro Shintani; Hiromitsu Awano; Takashi Sato 001; Jun Shiomi (QCE, 2024)

SecONN: An Optical Neural Network Framework with Concurrent Detection of Thermal Fault Injection Attacks. - Kota Nishida; Yoshihiro Midoh; Noriyuki Miura; Satoshi Kawakami; Jun Shiomi (CoRR, 2024)

StrideHD: A Binary Hyperdimensional Computing System Utilizing Window Striding for Image Classification. - Dehua Liang; Jun Shiomi; Noriyuki Miura; Hiromitsu Awano (IEEE Open J. Circuits Syst., 2024)

A Robust and Energy Efficient Hyperdimensional Computing System for Voltage-scaled Circuits. - Dehua Liang; Hiromitsu Awano; Noriyuki Miura; Jun Shiomi (ACM Trans. Embed. Comput. Syst., 2024)

Hardware Trojan Detection by Fine-grained Power Domain Partitioning. - Takahiro Ishikawa; Kose Yokooji; Yoshihiro Midoh; Noriyuki Miura; Michihiro Shintani; Jun Shiomi (ASP-DAC, 2025)

Cryo-HT: Hardware Trojan Activated at Cryogenic Temperatures. - Ayano Takaya; Ryuichi Nakajima; Jun Shiomi; Michihiro Shintani (ASP-DAC, 2025)

20.1 A 3.5×3.5mm2 1.47mW/ch 16-Channel MSS-CMOS Heterogeneous Multi-Modal-Gas-Sensor Chip Stack. - Kotaro Naruse; Naru Kato; Takuma Matsumori; Jun Shiomi; Yoshihiro Midoh; Tetsuya Hirose; Gaku Imamura; Genki Yoshikawa; Constantine Sideris; Noriyuki Miura (ISSCC, 2025)