Development of Image Recognition Processor Based on Configurable Processor. - Takashi Miyamori; Jun Tanabe; Yasuhiro Taniguchi; Kenji Furukawa; Tatsuo Kozakaya; Hiroaki Nakai; Yukimasa Miyamoto; Ken-ichi Maeda; Masataka Matsui (J. Robotics Mechatronics, 2005)

A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology. - Shuou Nomura; Fumihiko Tachibana; Tetsuya Fujita; Chen Kong Teh; Hiroyuki Usui; Fumiyuki Yamane; Yukimasa Miyamoto; Chaiyasit Kumtornkittikul; Hiroyuki Hara; Takahiro Yamashita; Jun Tanabe; Masaru Uchiyama; et al. (ISSCC, 2008)

Empirical Analysis of Travel Time Reliability Measures in Hanshin Expressway Network. - Akito Higatani; Toshihiko Kitazawa; Jun Tanabe; Yoshiki Suga; Ravi Sekhar; Yasuo Asakura (J. Intell. Transp. Syst., 2009)

A low power many-core SoC with two 32-core clusters connected by tree based NoC for multimedia applications. - Hui Xu; Jun Tanabe; Hiroyuki Usui; Soichiro Hosoda; Toru Sano; Kazumasa Yamamoto; Takeshi Kodaka; Nobuhiro Nonogaki; Nau Ozaki; Takashi Miyamori (VLSIC, 2012)

A near-future prediction method for low power consumption on a many-core processor. - Takeshi Kodaka; Akira Takeda; Shunsuke Sasaki; Akira Yokosawa; Toshiki Kizu; Takahiro Tokuyoshi; Hui Xu; Toru Sano; Hiroyuki Usui; Jun Tanabe; Takashi Miyamori; Nobu Matsumoto (DATE, 2013)

Development of low power many-core SoC for multimedia applications. - Takashi Miyamori; Hui Xu; Takeshi Kodaka; Hiroyuki Usui; Toru Sano; Jun Tanabe (DATE, 2013)

An evaluation of an energy efficient many-core SoC with parallelized face detection. - Hiroyuki Usui; Jun Tanabe; Toru Sano; Hui Xu; Takashi Miyamori (ASP-DAC, 2014)

Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters. - Takashi Miyamori; Hui Xu; Hiroyuki Usui; Soichiro Hosoda; Toru Sano; Kazumasa Yamamoto; Takeshi Kodaka; Nobuhiro Nonogaki; Nau Ozaki; Jun Tanabe (IEICE Trans. Electron., 2014)

18.2 A 1.9TOPS and 564GOPS/W heterogeneous multicore SoC with color-based object classification accelerator for image-recognition applications. - Jun Tanabe; Toru Sano; Yutaka Yamada; Tomoki Watanabe; Mayu Okumura; Manabu Nishiyama; Tadakazu Nomura; Kazushige Oma; Nobuhiro Sato; Moriyasu Banno; Hiroo Hayashi; Takashi Miyamori (ISSCC, 2015)

A 20.5TOPS and 217.3GOPS/mm2 Multicore SoC with DNN Accelerator and Image Signal Processor Complying with ISO26262 for Automotive Applications. - Yutaka Yamada; Toru Sano; Yasuki Tanabe; Yutaro Ishigaki; Soichiro Hosoda; Fumihiko Hyuga; Akira Moriya; Ryuji Hada; Atsushi Masuda; Masato Uchiyama; Tomohiro Koizumi; Takanori Tamai; et al. (ISSCC, 2019)

A 20.5 TOPS Multicore SoC With DNN Accelerator and Image Signal Processor for Automotive Applications. - Yutaka Yamada; Masato Uchiyama; Masashi Jobashi; Tomohiro Koizumi; Takanori Tamai; Nobuhiro Sato; Jun Tanabe; Katsuyuki Kimura; Yoshinari Ojima; Ryusuke Murakami; Takashi Yoshikawa; Toru Sano; et al. (IEEE J. Solid State Circuits, 2020)

Minecraft Video Aesthetics Quality Assessment Model. - Ryosuke Hasegawa; Ruck Thawonmas; Jun Tanabe; Lian Yu (IAIT, 2023)

Adaptive Background Music According to the Player's Arousal for DareFightingICE. - Jun Tanabe; Ibrahim Khan; Thai Van Nguyen 001; Chollakorn Nimpattanavong; Ruck Thawonmas (IAIT, 2023)