Compiler-guided register reliability improvement against soft errors. - Jun Yan 008; Wei Zhang 002 (EMSOFT, 2005)

Virtual Registers: Reducing Register Pressure Without Enlarging the Register File. - Jun Yan 008; Wei Zhang 002 (HiPEAC, 2007)

WCET analysis of instruction caches with prefetching. - Jun Yan 008; Wei Zhang 002 (LCTES, 2007)

Hybrid multi-core architecture for boosting single-threaded performance. - Jun Yan 008; Wei Zhang 002 (SIGARCH Comput. Archit. News, 2007)

Evaluating instruction cache vulnerability to transient errors. - Jun Yan 008; Wei Zhang 002 (SIGARCH Comput. Archit. News, 2007)

WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches. - Jun Yan 008; Wei Zhang 002 (IEEE Real-Time and Embedded Technology and Applications Symposium, 2008)

A time-predictable VLIW processor and its compiler support. - Jun Yan 008; Wei Zhang 002 (Real Time Syst., 2008)

Exploiting virtual registers to reduce pressure on real registers. - Jun Yan 008; Wei Zhang 002 (ACM Trans. Archit. Code Optim., 2008)

Analyzing the worst-case execution time for instruction caches with prefetching. - Jun Yan 008; Wei Zhang 002 (ACM Trans. Embed. Comput. Syst., 2008)

Accurately Estimating Worst-Case Execution Time for Multi-core Processors with Shared Direct-Mapped Instruction Caches. - Wei Zhang 002; Jun Yan 008 (RTCSA, 2009)

Optimizing Instruction Prefetching to Improve Worst-Case Performance for Real-Time Applications. - Yiqiang Ding; Jun Yan 008; Wei Zhang 002 (J. Comput. Sci. Eng., 2009)

Time-Predictable L2 Cache Design for High-Performance Real-Time Systems. - Jun Yan 008; Wei Zhang 002 (RTCSA, 2010)

Design and implementation of hybrid multicore simulators. - Jun Yan 008; Wei Zhang 002 (Int. J. Embed. Syst., 2010)

Bounding Worst-Case Performance for Multi-Core Processors with Shared L2 Instruction Caches. - Jun Yan 008; Wei Zhang 002 (J. Comput. Sci. Eng., 2011)

Computing and Reducing Transient Error Propagation in Registers. - Jun Yan 008; Wei Zhang 002 (J. Comput. Sci. Eng., 2011)

An Interference Matrix Based Approach to Bounding Worst-Case Inter-Thread Cache Interferences and WCET for Multi-Core Processors. - Jun Yan 008; Wei Zhang 002 (J. Comput. Sci. Eng., 2011)

Static Timing Analysis of Shared Caches for Multicore Processors. - Wei Zhang 002; Jun Yan 008 (J. Comput. Sci. Eng., 2012)

Priority L2 cache design for time predictability. - Jun Yan 008; Wei Zhang 002 (Int. J. Embed. Syst., 2016)