Domain fault model and coverage metric for SoC verification. - Chun Luo; Jun Yang 006; Gugang Gao; Longxing Shi (ISCAS (6), 2005)

Domain Strategy and Coverage Metric for Validation. - Chun Luo; Jun Yang 006; Longxing Shi; Xufan Wu; Yu Zhang (ISQED, 2005)

Bus Buffer Evaluation of Different Arbitration Algorithms. - Xufan Wu; Jun Yang 006; Longxing Shi (SoCC, 2005)

A Novel Fast-Lock-in Digitally Controlled Phase-Locked Loop. - Xin Chen 039; Jun Yang 006; Longxing Shi (IEICE Trans. Electron., 2008)

Area-efficient line-based two-dimensional discrete wavelet transform architecture without data buffer. - Peng Cao 002; Chao Wang 068; Jun Yang 006; Longxing Shi (ICME, 2009)

Analysis of Jitter in CMOS Ring Oscillators due to Power Supply Noise. - Xiaoying Deng; Xin Chen 039; Jun Yang 006; Jianhui Wu (IEICE Trans. Electron., 2009)

Extended Control Flow Graph Based Performance and Energy Consumption Optimization Using Scratch-Pad Memory. - Xuexiang Wang; Hanlai Pu; Jun Yang 006; Longxing Shi (J. Circuits Syst. Comput., 2009)

A Fast Locking All-Digital Phase-Locked Loop via Feed-Forward Compensation Technique. - Xin Chen 039; Jun Yang 006; Longxing Shi (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Exploration of Full HD Media Decoding on SDR Baseband Processor. - Chen Mei; Min Li 001; Peng Cao 002; Amir Amin; Chunshu Li; Sofie Pollin; Jun Yang 006 (SiPS, 2012)

Reconfiguration Process Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications. - Bo Liu 019; Peng Cao 002; Min Zhu 001; Jun Yang 006; Leibo Liu; Shaojun Wei; Longxing Shi (IEICE Trans. Inf. Syst., 2012)

Fast AdaBoost-Based Face Detection System on a Dynamically Coarse Grain Reconfigurable Architecture. - Jian Xiao; Jinguo Zhang; Min Zhu 001; Jun Yang 006; Longxing Shi (IEICE Trans. Inf. Syst., 2012)

Hierarchical representation of on-chip context to reduce reconfiguration time and implementation area for coarse-grained reconfigurable architecture. - Yansheng Wang; Leibo Liu; Shouyi Yin; Min Zhu 001; Peng Cao 002; Jun Yang 006; Shaojun Wei (Sci. China Inf. Sci., 2013)

On-chip long-term jitter measurement for PLL based on undersampling technique. - Zhikuang Cai; Haobo Xu; Shixuan Que; Weiwei Shan; Jun Yang 006 (IEICE Electron. Express, 2013)

Parallelism Analysis of H.264 Decoder and Realization on a Coarse-Grained Reconfigurable SoC. - Gugang Gao; Peng Cao 002; Jun Yang 006; Longxing Shi (IEICE Trans. Inf. Syst., 2013)

Hardware Software Co-design of H.264 Baseline Encoder on Coarse-Grained Dynamically Reconfigurable Computing System-on-Chip. - Hung K. Nguyen; Peng Cao 002; Xuexiang Wang; Jun Yang 006; Longxing Shi; Min Zhu 001; Leibo Liu; Shaojun Wei (IEICE Trans. Inf. Syst., 2013)

The Organization of On-Chip Data Memory in One Coarse-Grained Reconfigurable Architecture. - Yansheng Wang; Leibo Liu; Shouyi Yin; Min Zhu 001; Peng Cao 002; Jun Yang 006; Shaojun Wei (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Implementation of correlation power analysis attack on an FPGA DES design. - Jun Yang 006; Weiwei Shan; Junyin Liu; Huafang Sun (Int. J. Inf. Commun. Technol., 2013)

Exploration of Full HD Media Decoding on a Software Defined Radio Baseband Processor. - Chen Mei; Min Li 001; Peng Cao 002; Amir Amin; Chunshu Li; Jun Yang 006; Antoine Dejonghe; Liesbet Van der Perre; Longxing Shi; Sofie Pollin (IEEE Trans. Signal Process., 2013)

A Side-channel Analysis Resistant Reconfigurable Cryptographic Coprocessor Supporting Multiple Block Cipher Algorithms. - Weiwei Shan; Longxing Shi; Xingyuan Fu; Xiao Zhang; Chaoxuan Tian; Zhipeng Xu; Jun Yang 006; Jie Li (DAC, 2014)

An improved memory system simulator based on DRAMSim2. - Zhen Xie; Yang Zhang 132; Jun Yang 006; Longxing Shi (IEICE Electron. Express, 2014)

On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time. - Yansheng Wang; Leibo Liu; Shouyi Yin; Min Zhu 001; Peng Cao 002; Jun Yang 006; Shaojun Wei (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A GPS Bit Synchronization Method Based on Frequency Compensation. - Xinning Liu; Yuxiang Niu; Jun Yang 006; Peng Cao 002 (IEICE Trans. Commun., 2015)

An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding. - Leibo Liu; Dong Wang 040; Min Zhu 001; Yansheng Wang; Shouyi Yin; Peng Cao 002; Jun Yang 006; Shaojun Wei (IEEE Trans. Multim., 2015)

Correction to "An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding". - Leibo Liu; Dong Wang 040; Min Zhu 001; Yansheng Wang; Shouyi Yin; Peng Cao 002; Jun Yang 006; Shaojun Wei (IEEE Trans. Multim., 2015)

High performance and area efficiency design of global register file for coarse-grained reconfigurable cryptographic processor. - Ge Wei; Jinjiang Yang; Jun Yang 006 (IEICE Electron. Express, 2016)

An area-efficient design of reconfigurable S-box for parallel implementation of block ciphers. - Jinjiang Yang; Ge Wei; Peng Cao 002; Jun Yang 006 (IEICE Electron. Express, 2016)

Smartphone-Based Indoor Localization with Bluetooth Low Energy Beacons. - Yuan Zhuang 001; Jun Yang 006; You Li 001; Longning Qi; Naser El-Sheimy (Sensors, 2016)

HTD: A light-weight holosymmetrical transition detector based in-situ timing monitoring technique for wide-voltage-range in 40nm CMOS. - Wentao Dai; Weiwei Shan; Xinning Liu; Jun Yang 006 (A-SSCC, 2017)

A 0.44V-1.1V 9-transistor transition-detector and half-path error detection technique for low power applications. - Xinchao Shang; Weiwei Shan; Longxing Shi; Xing Wan; Jun Yang 006 (A-SSCC, 2017)

Analytical hold timing fixing for sub-threshold circuit based on its lognormal distribution. - Jingjing Guo; Min Wang; Jizhe Zhu; Xinning Liu; Jun Yang 006 (PATMOS, 2017)

Processing LSTM in memory using hybrid network expansion model. - Yu Gong; Tingting Xu; Bo Liu 019; Wei Ge; Jinjiang Yang; Jun Yang 006; Longxing Shi (SiPS, 2017)

An energy-efficient accelerator for hybrid bit-width DNNs. - Bo Liu 019; Xing Ruan; Mengwen Xia; Yu Gong; Jinjiang Yang; Wei Ge; Jun Yang 006 (SSCI, 2017)

In-Situ Timing Monitor-Based Adaptive Voltage Scaling System for Wide-Voltage-Range Applications. - Weiwei Shan; Longxing Shi; Jun Yang 006 (IEEE Access, 2017)

Analytical inverter chain's delay and its variation model for sub-threshold circuits. - Jingjing Guo; Jizhe Zhu; Min Wang; Jianxin Nie; Xinning Liu; Wei Ge; Jun Yang 006 (IEICE Electron. Express, 2017)

An improved timing error prediction monitor for wide adaptive frequency scaling. - Weiwei Shan; Xinning Liu; Minyi Lu; Shuai Shao; Zhikuang Cai; Jun Yang 006 (IEICE Electron. Express, 2017)

Efficient AES cipher on coarse-grained reconfigurable architecture. - Chao Wang 068; Peng Cao 002; Jun Yang 006 (IEICE Electron. Express, 2017)

Coarse-grained reconfigurable architecture with hierarchical context cache structure and management approach. - Chao Wang 068; Peng Cao 002; Bo Liu 019; Jun Yang 006 (IEICE Electron. Express, 2017)

Context Management Scheme Optimization of Coarse-Grained Reconfigurable Architecture for Multimedia Applications. - Peng Cao 002; Bo Liu 019; Jinjiang Yang; Jun Yang 006; Meng Zhang; Longxing Shi (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Stability and Variability Emphasized STT-MRAM Sensing Circuit With Performance Enhancement. - Menglin Han; Hao Cai 001; Jun Yang 006; Lirida A. B. Naviner; You Wang 002; Weisheng Zhao (APCCAS, 2018)

A 0.46V-1.1V Transition-Detector with In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in AES Accelerator. - Xinchao Shang; Weiwei Shan; Jiaming Xu; Minyi Lu; Yiming Xiang; Longxing Shi; Jun Yang 006 (A-SSCC, 2018)

Design and Optimization of Reconfigurable Data Path for Communication Baseband Signal Processing. - Shan-shan Zhu; Hai Qin; Bo Liu 019; Jun Yang 006 (CyberC, 2018)

A fast and robust failure analysis of memory circuits using adaptive importance sampling method. - Xiao Shi 001; Fengyuan Liu; Jun Yang 006; Lei He 001 (DAC, 2018)

Reliability Emphasized MTJ/CMOS Hybrid Circuit Towards Ultra-Low Power. - Hao Cai 001; Menglin Han; You Wang 002; Lirida A. B. Naviner; Xinning Liu; Jun Yang 006; Weisheng Zhao (DCIS, 2018)

An Energy-efficient Reconfigurable Hybrid DNN Architecture for Speech Recognition with Approximate Computing. - Bo Liu 019; Shisheng Guo; Hai Qin; Yu Gong; Jinjiang Yang; Wei Ge; Jun Yang 006 (DSP, 2018)

Compressed Sensing for Wideband HF Channel Estimation. - Elaine Crespo Marques; Nilson Maciel; Lirida A. B. Naviner; Hao Cai 001; Jun Yang 006 (ICFSP, 2018)

Enabling Resilient Voltage-Controlled MeRAM Using Write Assist Techniques. - Hao Cai 001; You Wang 002; Wang Kang 001; Lirida A. B. Naviner; Weiwei Shan; Jun Yang 006; Weisheng Zhao (ISCAS, 2018)

MRAM-on-FDSOI Integration: A Bit-Cell Perspective. - Hao Cai 001; You Wang 002; Wang Kang 001; Lirida A. B. Naviner; Xinning Liu; Jun Yang 006; Weisheng Zhao (ISVLSI, 2018)

A Power Analysis Attack Countermeasure Based on Random Execution. - Shenghua Chen; Wei Ge; Jinjiang Yang; Bo Liu 019; Jun Yang 006 (TrustCom/BigDataSE, 2018)

Noise Analysis and Modeling in Visible Light Communication Using Allan Variance. - Luchi Hua; Yuan Zhuang 001; Longning Qi; Jun Yang 006; Longxing Shi (IEEE Access, 2018)

A Low-Overhead Timing Monitoring Technique for Variation-Tolerant Near-Threshold Digital Integrated Circuits. - Weiwei Shan; Xinning Liu; Minyi Lu; Liang Wan; Jun Yang 006 (IEEE Access, 2018)

A Survey of Positioning Systems Using Visible LED Lights. - Yuan Zhuang 001; Luchi Hua; Longning Qi; Jun Yang 006; Pan Cao; Yue Cao 002; Yongpeng Wu 001; John Thompson 001; Harald Haas (IEEE Commun. Surv. Tutorials, 2018)

An improved BIJM circuit based on undersampling technique. - Zhikuang Cai; Haobo Xu; Jian Xiao; Jun Yang 006 (IEICE Electron. Express, 2018)

EERA-DNN: An energy-efficient reconfigurable architecture for DNNs with hybrid bit-width and logarithmic multiplier. - Zhen Wang 019; Mengwen Xia; Bo Liu 019; Xing Ruan; Yu Gong; Jinjiang Yang; Wei Ge; Jun Yang 006 (IEICE Electron. Express, 2018)

Guest Editorial: Special Issue on Toward Positioning, Navigation, and Location-Based Services (PNLBS) for Internet of Things. - Yuan Zhuang 001; Yue Cao 002; Naser El-Sheimy; Jun Yang 006 (IEEE Internet Things J., 2018)

A Pervasive Integration Platform of Low-Cost MEMS Sensors and Wireless Signals for Indoor Localization. - Yuan Zhuang 001; Jun Yang 006; Longning Qi; You Li 001; Yue Cao 002; Naser El-Sheimy (IEEE Internet Things J., 2018)

A Double Sensing Scheme With Selective Bitline Voltage Regulation for Ultralow-Voltage Timing Speculative SRAM. - Jun Yang 006; Hao Ji; Yichen Guo; Jizhe Zhu; Yuan Zhuang 001; Zhi Li; Xinning Liu; Longxing Shi (IEEE J. Solid State Circuits, 2018)

A Double Dwell High Sensitivity GPS Acquisition Scheme Using Binarized Convolution Neural Network. - Zhen Wang 019; Yuan Zhuang 001; Jun Yang 006; Hengfeng Zhang; Wei Dong; Min Wang; Luchi Hua; Bo Liu 019; Longxing Shi (Sensors, 2018)

HTD: A Light-Weight Holosymmetrical Transition Detector for Wide-Voltage-Range Variation Resilient ICs. - Wentao Dai; Weiwei Shan; Xinchao Shang; Xinning Liu; Hao Cai 001; Jun Yang 006 (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Timing Error Prediction AVFS With Detection Window Tuning for Wide-Operating-Range ICs. - Weiwei Shan; Xinchao Shang; Longxing Shi; Wentao Dai; Jun Yang 006 (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Low Overhead, Within-a-Cycle Adaptive Clock Stretching Circuit With Wide Operating Range in 40-nm CMOS. - Weiwei Shan; Liang Wan; Xinning Liu; Xinchao Shang; Wentao Dai; Shuai Shao; Jun Yang 006; Longxing Shi (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Statistical Current and Delay Model Based on Log-Skew-Normal Distribution for Low Voltage Region. - Peng Cao 002; Jiangping Wu; Zhiyuan Liu 011; Jingjing Guo; Jun Yang 006; Longxing Shi (ACM Great Lakes Symposium on VLSI, 2019)

Voltage-Controlled Magnetoelectric Memory Bit-cell Design With Assisted Body-bias in FD-SOI. - Hao Cai 001; Menglin Han; Weiwei Shan; Jun Yang 006; You Wang 002; Wang Kang 001; Weisheng Zhao (ACM Great Lakes Symposium on VLSI, 2019)

In-memory Processing based on Time-domain Circuit. - Yuyao Kong; Jun Yang 006 (ACM Great Lakes Symposium on VLSI, 2019)

A Statistical Timing Model for Low Voltage Design Considering Process Variation. - Peng Cao 002; Zhiyuan Liu 011; Jiangping Wu; Jingjing Guo; Jun Yang 006; Longxing Shi (ICCAD, 2019)

Deep Learning Approaches for Sparse Recovery in Compressive Sensing. - Elaine Crespo Marques; Nilson Maciel; Lirida A. B. Naviner; Hao Cai 001; Jun Yang 006 (ISPA, 2019)

Sandwich-RAM: An Energy-Efficient In-Memory BWN Architecture with Pulse-Width Modulation. - Jun Yang 006; Yuyao Kong; Zhen Wang 019; Yan Liu; Bo Wang 023; Shouyi Yin; Longxin Shi (ISSCC, 2019)

Pj-AxMTJ: Process-in-memory with Joint Magnetization Switching for Approximate Computing in Magnetic Tunnel Junction. - Hao Cai 001; Honglan Jiang; Menglin Han; Zhaohao Wang; You Wang 002; Jun Yang 006; Jie Han 001; Leibo Liu; Weisheng Zhao (ISVLSI, 2019)

RRS cache: a low voltage cache based on timing speculation SRAM with a reuse-aware cacheline remapping mechanism. - Xiaojing Shang; Ming Ling; Shan Shen; Tianxiang Shao; Jun Yang 006 (MEMSYS, 2019)

Comprehensive Pulse Shape Induced Failure Analysis in Voltage-Controlled MRAM. - Mingyue Liu; Hao Cai 001; Menglin Han; Lei Xie; Jun Yang 006; Lirida A. B. Naviner (NANOARCH, 2019)

REAL: Logic and Arithmetic Operations Embedded in RRAM for General-Purpose Computing. - Lei Xie; Hao Cai 001; Jun Yang 006 (NANOARCH, 2019)

A Self-Timing Voltage-Mode Sense Amplifier for STT-MRAM Sensing Yield Improvement. - Yongliang Zhou; Menglin Han; Mingyue Liu; Hao Cai 001; Bo Liu 019; Jun Yang 006 (NANOARCH, 2019)

Accurate and Efficient Interdependent Timing Model for Flip-Flop in Wide Voltage Region. - Peng Cao 002; Zhiyuan Liu 011; Jingjing Guo; Haoyu Pang; Jiangping Wu; Jun Yang 006 (NEWCAS, 2019)

Nonlinear Functions in Learned Iterative Shrinkage-Thresholding Algorithm for Sparse Signal Recovery. - Elaine Crespo Marques; Nilson Maciel; Lirida A. B. Naviner; Hao Cai 001; Jun Yang 006 (SiPS, 2019)

A 923 Gbps/W, 113-Cycle, 2-Sbox Energy-efficient AES Accelerator in 28nm CMOS. - Weiwei Shan; Ao Fan; Jiaming Xu; Jun Yang 006; Mingoo Seok (VLSI Circuits, 2019)

Lowering the Hit Latencies of Low Voltage Caches Based on the Cross-Sensing Timing Speculation SRAM. - Ming Ling; Xiaojing Shang; Shan Shen; Tianxiang Shao; Jun Yang 006 (IEEE Access, 2019)

A Review of Sparse Recovery Algorithms. - Elaine Crespo Marques; Nilson Maciel; Lirida A. B. Naviner; Hao Cai 001; Jun Yang 006 (IEEE Access, 2019)

Correlation of Gut Microbiome Between ASD Children and Mothers and Potential Biomarkers for Risk Assessment. - Ning Li; Junjie Yang; Jiaming Zhang; Cheng Liang 001; Ying Wang 001; Bin Chen; Changying Zhao; Jingwen Wang; Guangye Zhang; Dongmei Zhao; Yi Liu; Lehai Zhang; et al. (Genom. Proteom. Bioinform., 2019)

Low-Power Centimeter-Level Localization for Indoor Mobile Robots Based on Ensemble Kalman Smoother Using Received Signal Strength. - Yuan Zhuang 001; Qin Wang; Min Shi 001; Pan Cao; Longning Qi; Jun Yang 006 (IEEE Internet Things J., 2019)

An energy-efficient voice activity detector using deep neural networks and approximate computing. - Bo Liu 019; Zhen Wang 019; Shisheng Guo; Huazhen Yu; Yu Gong; Jun Yang 006; Longxing Shi (Microelectron. J., 2019)

The Integration of Photodiode and Camera for Visible Light Positioning by Using Fixed-Lag Ensemble Kalman Smoother. - Yuan Zhuang 001; Qin Wang; You Li 001; Zhouzheng Gao; Bingpeng Zhou; Longning Qi; Jun Yang 006; Ruizhi Chen; Naser El-Sheimy (Remote. Sens., 2019)

Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration. - Hao Cai 001; You Wang 002; Lirida Alves de Barros Naviner; Xinning Liu; Weiwei Shan; Jun Yang 006; Weisheng Zhao (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Wide-Voltage-Range Half-Path Timing Error-Detection System With a 9-Transistor Transition-Detector in 40-nm CMOS. - Weiwei Shan; Xinchao Shang; Xing Wan; Hao Cai 001; Chuan Zhang 001; Jun Yang 006 (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Visible Light Positioning and Navigation Using Noise Measurement and Mitigation. - Yuan Zhuang 001; Luchi Hua; Qin Wang; Yue Cao 002; Zhouzheng Gao; Longning Qi; Jun Yang 006; John Thompson 001 (IEEE Trans. Veh. Technol., 2019)

A Time-Domain Computing-in-Memory based Processor using Predictable Decomposed Convolution for Arbitrary Quantized DNNs. - Jianxun Yang; Yuyao Kong; Zhao Zhang; Zhuangzhi Liu; Jing Zhou; Yiqi Wang 005; Yonggang Liu; Chenfu Guo; Te Hu; Congcong Li; Leibo Liu; Jin Zhang; et al. (A-SSCC, 2020)

Modeling and Designing of a PVT Auto-tracking Timing-speculative SRAM. - Shan Shen; Tianxiang Shao; Ming Ling; Jun Yang 006; Longxing Shi (DATE, 2020)

Power-Efficient Approximate Multiplier Using Adaptive Error Compensation. - Zhixi Yang; Honglan Jiang; Xianbin Li; Jun Yang 006 (ACM Great Lakes Symposium on VLSI, 2020)

Statistical Timing Model for Subthreshold Circuit with Correlated Variation Consideration. - Jingjing Guo; Peng Cao 002; Mengxiao Li; Zhiyuan Liu 011; Jun Yang 006 (ISCAS, 2020)

14.1 A 510nW 0.41V Low-Memory Low-Computation Keyword-Spotting Chip Using Serial FFT-Based MFCC and Binarized Depthwise Separable Convolutional Neural Network in 28nm CMOS. - Weiwei Shan; Minhao Yang; Jiaming Xu; Yicheng Lu; Shuai Zhang; Tao Wang; Jun Yang 006; Longxing Shi; Mingoo Seok (ISSCC, 2020)

CATCAM: Constant-time Alteration Ternary CAM with Scalable In-Memory Architecture. - Dibei Chen; Zhaoshi Li; Tianzhu Xiong; Zhiwei Liu; Jun Yang 006; Shouyi Yin; Shaojun Wei; Leibo Liu (MICRO, 2020)

Towards an automated design flow for memristor based VLSI circuits. - Lei Xie; Hao Cai 001; Chao Wang 068; Jun Yang 006 (Integr., 2020)

A Bi-Directional, Zero-Latency Adaptive Clocking Circuit in a 28-nm Wide AVFS System. - Weiwei Shan; Wentao Dai; Liang Wan; Minyi Lu; Longxing Shi; Mingoo Seok; Jun Yang 006 (IEEE J. Solid State Circuits, 2020)

TG-SPP: A One-Transmission-Gate Short-Path Padding for Wide-Voltage-Range Resilient Circuits in 28-nm CMOS. - Weiwei Shan; Wentao Dai; Chuan Zhang 001; Hao Cai 001; Peiye Liu; Jun Yang 006; Longxing Shi (IEEE J. Solid State Circuits, 2020)

Machine Learning Assisted Side-Channel-Attack Countermeasure and Its Application on a 28-nm AES Circuit. - Weiwei Shan; Shuai Zhang; Jiaming Xu; Minyi Lu; Longxing Shi; Jun Yang 006 (IEEE J. Solid State Circuits, 2020)

Bandwidth-Enhanced Oversampling Successive Approximation Readout Technique for Low-Noise Power-Efficient MEMS Capacitive Accelerometer. - Longjie Zhong; Jun Yang 006; Donglai Xu; Xinquan Lai (IEEE J. Solid State Circuits, 2020)

A 22nm, 10.8 μ W/15.1 μ W Dual Computing Modes High Power-Performance-Area Efficiency Domained Background Noise Aware Keyword- Spotting Processor. - Bo Liu 019; Hao Cai 001; Zhen Wang 019; Yuhao Sun; Zeyu Shen 003; Wentao Zhu; Yan Li 056; Yu Gong; Wei Ge; Jun Yang 006; Longxing Shi (IEEE Trans. Circuits Syst., 2020)

MTJ-LRB: Proposal of MTJ-Based Loop Replica Bitline as MRAM Device-Circuit Interaction for PVT-Robust Sensing. - Yongliang Zhou; Hao Cai 001; Bo Liu 019; Weisheng Zhao; Jun Yang 006 (IEEE Trans. Circuits Syst., 2020)

A Self-Timed Voltage-Mode Sensing Scheme With Successive Sensing and Checking for STT-MRAM. - Yongliang Zhou; Hao Cai 001; Lei Xie; Menglin Han; Mingyue Liu; Shi Xu; Bo Liu 019; Weisheng Zhao; Jun Yang 006 (IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020)

TS Cache: A Fast Cache With Timing-Speculation Mechanism Under Low Supply Voltages. - Shan Shen; Tianxiang Shao; Xiaojing Shang; Yichen Guo; Ming Ling; Jun Yang 006; Longxing Shi (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Challenge and Trend of SRAM Based Computation-in-Memory Circuits for AI Edge Devices. - Xin Si; Yongliang Zhou; Jun Yang 006; Meng-Fan Chang (ASICON, 2021)

An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator without Accuracy Loss in 28nm CMOS. - Ziyu Li; Weiwei Shan; Chengjun Wu; Haitao Ge; Jun Yang 006 (A-SSCC, 2021)

Design Methodology towards High-Precision SRAM based Computation-in-Memory for AI Edge Devices. - Tianzhu Xiong; Yongliang Zhou; Yuyao Kong; Bo Wang 023; An Guo 001; Yufei Wang; Chen Xue; Haiming Hsu; Xin Si; Jun Yang 006 (ISOCC, 2021)

29.8 115nA@3V ULPMark-CP Score 1205 SCVR-Less Dynamic Voltage-Stacking Scheme for IoT MCU. - Xiaomin Li; Yibo Xu; Lizheng Ren; Weiwei Ge; Jianlong Cai; Xinning Liu; Jun Yang 006 (ISSCC, 2021)

Cryogenic In-MRAM Computing. - Yaoru Hou; We Ge; Yanan Guo 004; Lirida A. B. Naviner; You Wang 002; Bo Liu 019; Jun Yang 006; Hao Cai 001 (NANOARCH, 2021)

A survey of in-spin transfer torque MRAM computing. - Hao Cai 001; Bo Liu 019; Juntong Chen; Lirida A. B. Naviner; Yongliang Zhou; Zhen Wang 019; Jun Yang 006 (Sci. China Inf. Sci., 2021)

A 510-nW Wake-Up Keyword-Spotting Chip Using Serial-FFT-Based MFCC and Binarized Depthwise Separable CNN in 28-nm CMOS. - Weiwei Shan; Minhao Yang; Tao Wang; Yicheng Lu; Hao Cai 001; Lixuan Zhu; Jiaming Xu; Chengjun Wu; Longxing Shi; Jun Yang 006 (IEEE J. Solid State Circuits, 2021)

TIMAQ: A Time-Domain Computing-in-Memory-Based Processor Using Predictable Decomposed Convolution for Arbitrary Quantized DNNs. - Jianxun Yang; Yuyao Kong; Zhao Zhang; Zhuangzhi Liu; Jing Zhou; Yiqi Wang 005; Yonggang Liu; Chenfu Guo; Te Hu; Congcong Li; Leibo Liu; Jin Zhang; et al. (IEEE J. Solid State Circuits, 2021)

Semi-Analytical Path Delay Variation Model With Adjacent Gates Decorrelation for Subthreshold Circuits. - Jingjing Guo; Peng Cao 002; Mengxiao Li; Yu Gong; Zhiyuan Liu 011; Geng Bai; Jun Yang 006 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

A Design of Timing Speculation SRAM-Based L1 Caches With PVT Autotracking Under Near-Threshold Voltages. - Ming Ling; Qingde Lin; Ke Tan 004; Tianxiang Shao; Shan Shen; Jun Yang 006 (IEEE Trans. Very Large Scale Integr. Syst., 2021)

FusionVLP: The Fusion of Photodiode and Camera for Visible Light Positioning. - Luchi Hua; Yuan Zhuang 001; You Li 001; Qin Wang; Bingpeng Zhou; Longning Qi; Jun Yang 006; Yue Cao 002; Harald Haas (IEEE Trans. Veh. Technol., 2021)

Approximate Computing for Energy-Constrained DNN-Based Speech Recognition. - Bo Liu 019; Hao Cai 001; Zhen Wang 019; Jun Yang 006 (Approximate Computing, 2022)

A Quantization Model Based on a Floating-point Computing-in-Memory Architecture. - Xi Chen 107; An Guo 001; Xinbing Xu; Xin Si; Jun Yang 006 (APCCAS, 2022)

TICA: A 0.3V, Variation-Resilient 64-Stage Deeply-Pipelined Bitcoin Mining Core with Timing Slack Inference and Clock Frequency Adaption. - Jieyu Li; Weifeng He; Bo Zhang 105; Guanghui He; Jun Yang 006; Mingoo Seok (CICC, 2022)

MPAM: Reliable, Low-Latency, Near-Threshold-Voltage Multi-Voltage/Frequency-Domain Network-on-Chip with Metastability Risk Prediction and Mitigation. - Chuxiong Lin; Weifeng He; Yannan Sun; Lin Shao; Bo Zhang 105; Jun Yang 006; Mingoo Seok (CICC, 2022)

High-performance placement for large-scale heterogeneous FPGAs with clock constraints. - Ziran Zhu; Yangjie Mei; Zijun Li 005; Jingwen Lin; Jianli Chen; Jun Yang 006; Yao-Wen Chang (DAC, 2022)

Triple-Skipping Near-MRAM Computing Framework for AIoT Era. - Juntong Chen; Hao Cai 001; Bo Liu 019; Jun Yang 006 (DATE, 2022)

A Target-Separable BWN Inspired Speech Recognition Processor with Low-power Precision-adaptive Approximate Computing. - Bo Liu 019; Hao Cai 001; Xuan Zhang; Haige Wu; Anfeng Xue; Zilong Zhang; Zhen Wang 019; Jun Yang 006 (DATE, 2022)

Graph Convolutional Network Empowered Indoor Localization Method via Aggregating MIMO CSI. - Hao Gu; Jun Yang 006; Zhengran He; Guan Gui 001; Haris Gacanin (GLOBECOM, 2022)

A 28nm, 4.69TOPS/W Training, 2.34µJ/lmage Inference, on-chip Training Accelerator with Inference-compatible Back Propagation. - Haitao Ge; Weiwei Shan; Yicheng Lu; Jun Yang 006 (ICTA, 2022)

ShareFloat CIM: A Compute-In-Memory Architecture with Floating-Point Multiply-and-Accumulate Operations. - An Guo 001; Yongliang Zhou; Bo Wang 023; Tianzhu Xiong; Chen Xue; Yufei Wang; Xin Si; Jun Yang 006 (ISCAS, 2022)

SNNIM: A 10T-SRAM based Spiking-Neural-Network-In-Memory architecture with capacitance computation. - Bo Wang 023; Chen Xue; Han Liu; Xiang Li; Anran Yin; Zhongyuan Feng; Yuyao Kong; Tianzhu Xiong; Haiming Hsu; Yongliang Zhou; An Guo 001; Yufei Wang; et al. (ISCAS, 2022)

Self-compensation tensor multiplication unit for adaptive approximate computing in low-power CNN processing. - Bo Liu 019; Zilong Zhang; Hao Cai 001; Reyuan Zhang; Zhen Wang 019; Jun Yang 006 (Sci. China Inf. Sci., 2022)

SmartFPS: Neural Network based Wireless-inertial fusion positioning system. - Luchi Hua; Jun Yang 006 (CoRR, 2022)

SCVR-Less Dynamic Voltage-Stacking Scheme for IoT MCU. - Xinning Liu; Xiaomin Li; Huanqing Zhang; Chenyang Li; Lizheng Ren; Qing Chen; Yibo Xu; Jun Yang 006 (IEEE J. Solid State Circuits, 2022)

An Efficient BCNN Deployment Method Using Quality-Aware Approximate Computing. - Bo Liu 019; Ziyu Wang; Xuetao Wang; Renyuan Zhang; Anfeng Xue; Qiao Shen 001; Na Xie; Yu Gong; Zhen Wang 019; Jun Yang 006; Hao Cai 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Proposal of Analog In-Memory Computing With Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell. - Hao Cai 001; Yanan Guo 004; Bo Liu 019; Mingyang Zhou 002; Juntong Chen; Xinning Liu; Jun Yang 006 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

More is Less: Domain-Specific Speech Recognition Microprocessor Using One-Dimensional Convolutional Recurrent Neural Network. - Bo Liu 019; Hao Cai 001; Zilong Zhang; Xiaoling Ding; Ziyu Wang; Yu Gong; Weiqiang Liu 001; Jinjiang Yang; Zhen Wang 019; Jun Yang 006 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Optimal Edge Nodes Deployment With Multi Association for Smart Health. - Chao Chen 030; Peng Li; Xin Jian; Langyun Wu; Jun Yang 006 (IEEE Trans. Mol. Biol. Multi Scale Commun., 2022)

A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference. - Hao Cai 001; Zhongjian Bian; Yaoru Hou; Yongliang Zhou; Jia-Le Cui; Yanan Guo 004; Xiaoyun Tian; Bo Liu 019; Xin Si; Zhen Wang 019; Jun Yang 006; Weiwei Shan (ISSCC, 2023)

A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs. - An Guo 001; Xin Si; Xi Chen 107; Fangyuan Dong; Xingyu Pu; Dongqi Li; Yongliang Zhou; Lizheng Ren; Yeyang Xue; Xueshan Dong; Hui Gao; Yiran Zhang; et al. (ISSCC, 2023)

A 28nm Horizontal-Weight-Shift and Vertical-feature-Shift-Based Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks. - Bo Wang 023; Chen Xue; Zhongyuan Feng; Zhaoyang Zhang; Han Liu; Lizheng Ren; Xiang Li; Anran Yin; Tianzhu Xiong; Yeyang Xue; Shengnan He; Yuyao Kong; et al. (ISSCC, 2023)

An Ultra-Low-Voltage 2.4-GHz Flicker-Noise-Free RF Receiver Front End Based on Switched-Capacitor Hybrid TIA With 4.5-dB NF and 11.5-dBm OIP3. - Chao Chen 030; Dan Huang; Yan Zhao; Yuemin Jin; Jun Yang 006 (IEEE J. Solid State Circuits, 2023)

An efficient path delay variability model for wide-voltage-range digital circuits. - Weiwei Shan; Yuqiang Cui; Wentao Dai; Xinning Liu; Jingjing Guo; Peng Cao 002; Jun Yang 006 (Sci. China Inf. Sci., 2023)

AAD-KWS: A Sub-μ W Keyword Spotting Chip With an Acoustic Activity Detector Embedded in MFCC and a Tunable Detection Window in 28-nm CMOS. - Weiwei Shan; Junyi Qian; Lixuan Zhu; Jun Yang 006; Cheng Huang 005; Hao Cai 001 (IEEE J. Solid State Circuits, 2023)

Evaluation Platform of Time-Domain Computing-in-Memory Circuits. - Yuyao Kong; Xi Chen 107; Xin Si; Jun Yang 006 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Beyond Eliminating Timing Margin: An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator Without Accuracy Loss. - Zhengguo Shen; Weiwei Shan; Yuxuan Du; Ziyu Li; Jun Yang 006 (IEEE J. Solid State Circuits, 2023)

Multiplication Circuit Architecture for Error- Tolerant CNN-Based Keywords Speech Recognition. - Bo Liu 019; Hao Cai 001; Zilong Zhang; Xiaoling Ding; Renyuan Zhang; Yu Gong; Zhen Wang 019; Wei Ge; Jun Yang 006 (IEEE Des. Test, 2023)

SmartFPS: Neural network based wireless-inertial fusion positioning system. - Luchi Hua; Yuan Zhuang 001; Jun Yang 006 (Frontiers Neurorobotics, 2023)

A 0.55V 10-Bit 100-MS/s SAR ADC With 3.6-fJ/Conversion-Step in 28nm CMOS for RF Receivers. - Yan Zhao; Chao Chen 030; Jun Yang 006 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Multi-sensor integrated navigation/positioning systems using data fusion: From analytics-based to learning-based approaches. - Yuan Zhuang 001; Xiao Sun 009; You Li 001; Jianzhu Huai; Luchi Hua; Xiansheng Yang; Xiaoxiang Cao; Peng Zhang 042; Yue Cao 002; Longning Qi; Jun Yang 006; Nashwa El-Bendary; et al. (Inf. Fusion, 2023)

Efficient and Accurate ECO Leakage Optimization Framework With GNN and Bidirectional LSTM. - Peng Cao 002; Guoqing He; Wenjie Ding; Zhanhua Zhang; Kai Wang; Jun Yang 006 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

From macro to microarchitecture: reviews and trends of SRAM-based compute-in-memory circuits. - Zhaoyang Zhang; Jinwu Chen; Xi Chen 107; An Guo 001; Bo Wang 023; Tianzhu Xiong; Yuyao Kong; Xingyu Pu; Shengnan He; Xin Si; Jun Yang 006 (Sci. China Inf. Sci., 2023)

Triplet MatchNet Based Indoor Position Method Using CSI Fingerprint Similarity Comparison. - Hao Gu; Jun Yang 006; Guan Gui 001; Haris Gacanin (IEEE Trans. Veh. Technol., 2023)

Variational Label-Correlation Enhancement for Congestion Prediction. - Biao Liu; Congyu Qiao; Ning Xu 009; Xin Geng 001; Ziran Zhu; Jun Yang 006 (ASPDAC, 2024)

A 28nm 128-kb Exponent- and Mantissa-Computation-InMemory Dual-macro for Floating-point and INT CNNs. - An Guo 001; Xueshan Dong; Fangyuan Dong; Dongqi Li; Yiran Zhang; Jingmin Zhang; Yuchen Tang; Yuhui Shi; Xiao Tan; Bo Liu 019; Weiwei Shan; Hao Cai 001; et al. (A-SSCC, 2024)

A 28nm 16kb Aggregation and Combination Computing-in-Memory Macro with Dual-level Sparsity Modulation and Sparse-Tracking ADCs for GCNs. - Zhaoyang Zhang; Zhichao Liu; Feiran Liu; Yinhai Gao; Yuchen Ma; Yutong Zhang; An Guo 001; Tianzhu Xiong; Jinwu Chen; Xi Chen 107; Bo Wang 023; Yuchen Tang; et al. (CICC, 2024)

Late Breaking Results: Routability-Driven FPGA Macro Placement Considering Complex Cascade Shape and Region Constraints. - Hao Gu; Jian Gu; Keyu Peng; Jun Yang 006; Ziran Zhu (DAC, 2024)

22 nm Ultra-Low Power MCU with 43.5nW/KB Sleep Retention Power for Automotive Grade-1 Applications. - Yibo Liu; Wen Wang; Hongjin Zhu; Longning Qi; Bo Liu 019; Xinning Liu; Jun Yang 006; Hao Cai 001 (ICTA, 2024)

34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs. - An Guo 001; Xi Chen 107; Fangyuan Dong; Jinwu Chen; Zhihang Yuan; Xing Hu 010; Yuanpeng Zhang; Jingmin Zhang; Yuchen Tang; Zhican Zhang; Gang Chen 023; Dawei Yang; et al. (ISSCC, 2024)

14.2 Proactive Voltage Droop Mitigation Using Dual-Proportional-Derivative Control Based on Current and Voltage Prediction Applied to a Multicore Processor in 28nm CMOS. - Weiwei Shan; Kaize Zhou; Keran Li; Yuxuan Du; Zhuo Chen; Junyi Qian; Haitao Ge; Jun Yang 006; Xin Si (ISSCC, 2024)

CATCAM: a 28 nm constant-time alteration TCAM enabling less than 50 ns update latency. - Chenchen Deng; Tianzhu Xiong; Zhaoshi Li; Zhiwei Liu; Yao Wang; Jianfeng Zhu 001; Jun Yang 006; Shaojun Wei; Leibo Liu (Sci. China Inf. Sci., 2024)

ChipExpert: The Open-Source Integrated-Circuit-Design-Specific Large Language Model. - Ning Xu 009; Zhaoyang Zhang; Lei Qi 001; Wensuo Wang; Chao Zhang; Zihao Ren; Huaiyuan Zhang; Xin Cheng; Yanqi Zhang; Zhichao Liu; Qingwen Wei; Shiyang Wu; et al. (CoRR, 2024)

A 55 μ W 2.4 GHz wake-up receiver with offset-based peak detection achieving -90dBm sensitivity for IoT applications. - Yan Zhao; Chao Chen 030; Jun Yang 006 (Microelectron. J., 2024)

An Effective Routing Refinement Algorithm Based on Incremental Replacement and Rerouting. - Ziran Zhu; Fuheng Shen; Yangjie Mei; Jianli Chen; Jun Yang 006 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

TICA: Timing Slack Inference and Clock Frequency Adaption Technique for a Deeply Pipelined Near-Threshold-Voltage Bitcoin Mining Core. - Jieyu Li; Weifeng He; Bo Zhang 105; Guanghui He; Jing Jin 005; Jun Yang 006; Mingoo Seok (IEEE J. Solid State Circuits, 2024)

A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-Voltage Multivoltage/ Frequency-Domain Network-on-Chip. - Chuxiong Lin; Weifeng He; Yanan Sun 003; Lin Shao; Bo Zhang 105; Jun Yang 006; Mingoo Seok (IEEE J. Solid State Circuits, 2024)

High-Performance Placement Engine for Modern Large-Scale FPGAs With Heterogeneity and Clock Constraints. - Ziran Zhu; Yangjie Mei; Kangkang Deng; Huan He; Jianli Chen; Jun Yang 006; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Intrinsic MRAM Properties Enable Security Circuits. - Haoran Du; You Wang 002; Jun Yang 006; Hao Cai 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

High-Performance 3-D Placement Engine With Physical-Aware Incremental Partitioning. - Ziran Zhu; Yuejian Shi; Yangjie Mei; Fuheng Shen; Hong Liu; Jun Yang 006 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 0.65 V 4 dB NF 2.4 GHz Sub-Passive RF Down-Converter With Trans-Frequency Current-Reusing Scheme Achieving Low Flicker Noise and High Linearity. - Yan Zhao; Chao Chen 030; Jun Yang 006 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

LAMPlace: Legalization-Aided Reinforcement Learning-Based Macro Placement for Mixed-Size Designs With Preplaced Blocks. - Hao Gu; Jian Gu; Keyu Peng; Ziran Zhu; Ning Xu 009; Xin Geng 001; Jun Yang 006 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 28-nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs. - An Guo 001; Chen Xi; Fangyuan Dong; Xingyu Pu; Dongqi Li; Jingmin Zhang; Xueshan Dong; Hui Gao; Yiran Zhang; Bo Wang 023; Jun Yang 006; Xin Si (IEEE J. Solid State Circuits, 2024)

A 40nm 4Mb High-Reliability STT-MRAM Achieving 18ns Write-Time and 94.9% Wafer-Level-Die-Yield Across -55°C-to-125°C. - Yaoru Hou; Haoran Du; Jiongzhe Su; Yibo Liu; Zhenghan Fang; Jia-Le Cui; Shuyu Wang; Chenxing Liu-Sun; Xuezhao Wu; Zhihua Xiao; Bo Liu 019; Xin Si; et al. (CICC, 2025)

A 52.03TOPS/W DCIM-Based Accelerator with FlashAttention and Sparsity-Aware Alignment for LLMs. - Bo Liu 019; Xingyu Xu 008; Yang Zhang 132; Xilong Kang; Qingwen Wei; Zihan Zou; Jun Yang 006; Hao Cai 001; Xin Si (CICC, 2025)

LAD: Efficient Accelerator for Generative Inference of LLM with Locality Aware Decoding. - Haoran Wang 012; Yuming Li; Haobo Xu; Ying Wang 001; Liqi Liu; Jun Yang 006; Yinhe Han 001 (HPCA, 2025)

14.6 A 28nm 64kb Bit-Rotated Hybrid-CIM Macro with an Embedded Sign-Bit-Processing Array and a Multi-Bit-Fusion Dual-Granularity Cooperative Quantizer. - Xi Chen 107; Shaochen Li; Zhican Zhang; Wentao Zheng; Xiao Tan; Yuchen Tang; Yuhui Shi; Lizheng Ren; Yibo Mai; Feiran Liu; Jinwu Chen; Zhaoyang Zhang; et al. (ISSCC, 2025)

14.7 NeuroPilot: A 28nm, 69.4fJ/node and 0.22ns/node, 32×32 Mimetic-Path-Searching CIM-Macro with Dynamic-Logic Pilot PE and Dual-Direction Searching. - An Guo 001; Jingmin Zhang; Xingyu Pu; Yi Yang 001; Defa Wu; Yuchen Tang; Yuhui Shi; Yinghai Gao; Zhichao Liu; Bo Wang 023; Tianzhu Xiong; Zhaoyang Zhang; et al. (ISSCC, 2025)

14.3 A 28nm 17.83-to-62.84TFLOPS/W Broadcast-Alignment Floating-Point CIM Macro with Non-Two's-Complement MAC for CNNs and Transformers. - Xing Wang; Tianhui Jiao; Yi Yang 001; Shaochen Li; Dongqi Li; An Guo 001; Yuhui Shi; Yuchen Tang; Jinwu Chen; Zhican Zhang; Zhichao Liu; Bo Liu 019; et al. (ISSCC, 2025)

VCD-CIM: A Vertical-Compute-Decode Digital Computing-In-Memory Area-Efficient Macro for Vector-Wise Computation With Variable Accumulation Length. - Bo Wang 023; Xiaoxue Zhong; Jun Yang 006 (IEEE Access, 2025)

A Proactive Droop Mitigation Technique Using Dual-Proportional-Derivative Controller Based on Current and Voltage Prediction. - Kaize Zhou; Weiwei Shan; Keran Li; Zhuo Chen; Haitao Ge; Jun Yang 006 (IEEE J. Solid State Circuits, 2025)

A Hybrid Domain and Pipelined Analog Computing Chain for MVM Computation. - Tianzhu Xiong; Yuyang Ye 001; Xin Si; Jun Yang 006 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A 28-nm 16-kb Aggregation and Combination Computing-in-Memory Macro With Dual-Level Sparsity Modulation and Sparse-Tracking ADCs for GCNs. - Zhaoyang Zhang; Yanqi Zhang; Feiran Liu; Zhichao Liu; Yinhai Gao; Yuchen Ma; Yutong Zhang; An Guo 001; Tianzhu Xiong; Jinwu Chen; Xi Chen 107; Bo Wang 023; et al. (IEEE J. Solid State Circuits, 2025)

ForgeEDA: A Comprehensive Multimodal Dataset for Advancing EDA. - Zhengyuan Shi; Zeju Li; Chengyu Ma; Yunhao Zhou; Ziyang Zheng; Jiawei Liu 006; Hongyang Pan; Lingfeng Zhou; Kezhi Li; Jiaying Zhu; Lingwei Yan; Zhiqiang He; et al. (CoRR, 2025)

Dual Multimodal Fusions With Convolution and Transformer Layers for VLSI Congestion Prediction. - Hao Gu; Youwen Wang; Xinglin Zheng; Keyu Peng; Ziran Zhu; Jianli Chen; Jun Yang 006 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs. - Chenchen Zhao; Zhengyuan Shi; Xiangyu Wen; Chengjie Liu; Yi Liu; Yunhao Zhou; Yuxiang Zhao; Hefei Feng; Yinan Zhu; Gwok-Waa Wan; Xin Cheng; Weiyu Chen; et al. (CoRR, 2025)