A Highly Efficient FC-SAN Based on Load Stream. - Jiwu Shu; Jun Yao 001; Changdong Fu; Weimin Zheng (APPT, 2003)

Program Phase Detection Based Dynamic Control Mechanisms for Pipeline Stage Unification Adoption. - Jun Yao 001; Hajime Shimada; Yasuhiko Nakashima; Shin-ichiro Mori; Shinji Tomita (ISHPC, 2005)

Distributed Storage Cluster Design for Remote Mirroring Based on Storage Area Network. - Jun Yao 001; Jiwu Shu; Weimin Zheng (J. Comput. Sci. Technol., 2007)

Optimal pipeline depth with pipeline stage unification adoption. - Jun Yao 001; Shinobu Miwa; Hajime Shimada; Shinji Tomita (SIGARCH Comput. Archit. News, 2007)

A Dynamic Control Mechanism for Pipeline Stage Unification by Identifying Program Phases. - Jun Yao 001; Shinobu Miwa; Hajime Shimada; Shinji Tomita (IEICE Trans. Inf. Syst., 2008)

An Instruction Scheduler for Dynamic ALU Cascading Adoption. - Jun Yao 001; Kosuke Ogata; Hajime Shimada; Shinobu Miwa; Hiroshi Nakashima; Shinji Tomita (Inf. Media Technol., 2009)

A Stage-Level Recovery Scheme in Scalable Pipeline Modules for High Dependability. - Jun Yao 001; Hajime Shimada; Kazutoshi Kobayashi (IWIA, 2010)

A Minimal Roll-Back Based Recovery Scheme for Fault Toleration in Pipeline Processors. - Jun Yao 001; Ryoji Watanabe; Takashi Nakada; Hajime Shimada; Yasuhiko Nakashima; Kazutoshi Kobayashi (PRDC, 2010)

An efficient and reliable 1.5-way processor by fusion of space and time redundancies. - Jun Yao 001; Ryoji Watanabe; Kazuhiro Yoshimura; Takashi Nakada; Hajime Shimada; Yasuhiko Nakashima (DSN Workshops, 2011)

LAPP: A Low Power Array Accelerator with Binary Compatibility. - Naveen Devisetti; Takuya Iwakami; Kazuhiro Yoshimura; Takashi Nakada; Jun Yao 001; Yasuhiko Nakashima (IPDPS Workshops, 2011)

An Instruction Mapping Scheme for FU Array Accelerator. - Kazuhiro Yoshimura; Takuya Iwakami; Takashi Nakada; Jun Yao 001; Hajime Shimada; Yasuhiko Nakashima (IEICE Trans. Inf. Syst., 2011)

A Fine-Grained Runtime Power/Performance Optimization Method for Processors with Adaptive Pipeline Depth. - Jun Yao 001; Shinobu Miwa; Hajime Shimada; Shinji Tomita (J. Comput. Sci. Technol., 2011)

Introducing OVP awareness to achieve an efficient permanent defect locating. - Tanvir Ahmed 004; Jun Yao 001; Yasuhiko Nakashima (NANOARCH, 2012)

RazorProtector: Maintaining Razor DVS Efficiency in Large IR-Drop Zones by an Adaptive Redundant Data-Path. - Yukihiro Sasagawa; Jun Yao 001; Takashi Nakada; Yasuhiko Nakashima (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

HW/SW approaches to accelerate GRAPES in an FU array. - Wei Wang 332; Jun Yao 001; Youhui Zhang; Wei Xue 003; Yasuhiko Nakashima; Weimin Zheng (COOL Chips, 2013)

Selective Check of Data-Path for Effective Fault Tolerance. - Tanvir Ahmed 004; Jun Yao 001; Yuko Hara-Azumi; Shigeru Yamashita; Yasuhiko Nakashima (IEICE Trans. Inf. Syst., 2013)

A flexibly fault-tolerant FU array processor and its self-tuning scheme to locate permanently defective unit. - Jun Yao 001; Yasuhiko Nakashima; Mitsutoshi Saito; Yohei Hazama; Ryosuke Yamanaka (COOL Chips, 2014)

A globally asynchronous locally synchronous DMR architecture for aggressive low-power fault toleration. - Yuttakon Yuttakonkit; Jun Yao 001; Yasuhiko Nakashima (COOL Chips, 2014)

Understanding Variations for Better Adjusting Parallel Supplemental Redundant Executions to Tolerate Timing Faults. - Yukihiro Sasagawa; Jun Yao 001; Yasuhiko Nakashima (IEICE Trans. Inf. Syst., 2014)

A Tightly Coupled General Purpose Reconfigurable Accelerator LAPP and Its Power States for HotSpot-Based Energy Reduction. - Jun Yao 001; Yasuhiko Nakashima; Naveen Devisetti; Kazuhiro Yoshimura; Takashi Nakada (IEICE Trans. Inf. Syst., 2014)

A Flexible, Self-Tuning, Fault-Tolerant Functional Unit Array Processor. - Jun Yao 001; Yasuhiko Nakashima; Mitsutoshi Saito; Yohei Hazama; Ryosuke Yamanaka (IEEE Micro, 2014)

Lowering the complexity of k-means clustering by BFS-dijkstra method for graph computing. - Anna Zhang; Jun Yao 001; Yasuhiko Nakashima (COOL Chips, 2015)

A CGRA-Based Approach for Accelerating Convolutional Neural Networks. - Masakazu Tanomoto; Shinya Takamaeda-Yamazaki; Jun Yao 001; Yasuhiko Nakashima (MCSoC, 2015)

Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators. - Yoshikazu Inagaki; Shinya Takamaeda-Yamazaki; Jun Yao 001; Yasuhiko Nakashima (IEICE Trans. Inf. Syst., 2015)