A system-on-chip EPC Gen-2 passive UHF RFID tag with embedded temperature sensor. - Jun Yin 001; Jun Yi; Man Kay Law; Yunxiao Ling; Man Chiu Lee; Kwok Ping Ng; Bo Gao; Howard C. Luong; Amine Bermak; Mansun Chan; Wing-Hung Ki; Chi-Ying Tsui; et al. (ISSCC, 2010)

A System-on-Chip EPC Gen-2 Passive UHF RFID Tag With Embedded Temperature Sensor. - Jun Yin 001; Jun Yi; Matthew K. Law; Yunxiao Ling; Man Chiu Lee; Kwok Ping Ng; Bo Gao; Howard C. Luong; Amine Bermak; Mansun Chan; Wing-Hung Ki; Chi-Ying Tsui; et al. (IEEE J. Solid State Circuits, 2010)

A 57.5-to-90.1GHz magnetically-tuned multi-mode CMOS VCO. - Jun Yin 001; Howard C. Luong (CICC, 2012)

A CMOS 21-48GHz fractional-N synthesizer employing ultra-wideband injection-locked frequency multipliers. - Alvin Li; Shiyuan Zheng; Jun Yin 001; Howard C. Luong; Xun Luo (CICC, 2013)

A 57.5-90.1-GHz Magnetically Tuned Multimode CMOS VCO. - Jun Yin 001; Howard C. Luong (IEEE J. Solid State Circuits, 2013)

A 0.37-to-46.5GHz frequency synthesizer for software-defined radios in 65nm CMOS. - Jun Yin 001; Howard C. Luong (VLSIC, 2014)

A 21-48 GHz Subharmonic Injection-Locked Fractional-N Frequency Synthesizer for Multiband Point-to-Point Backhaul Communications. - Alvin Li; Shiyuan Zheng; Jun Yin 001; Xun Luo; Howard C. Luong (IEEE J. Solid State Circuits, 2014)

A high-Q spiral inductor with dual-layer patterned floating shield in a class-B VCO achieving a 190.5-dBc/Hz FoM. - Chee-Cheow Lim; Harikrishnan Ramiah; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (ISCAS, 2016)

2.7 A 0.003mm2 1.7-to-3.5GHz dual-mode time-interleaved ring-VCO achieving 90-to-150kHz 1/f3 phase-noise corner. - Jun Yin 001; Pui-In Mak; Franco Maloberti; Rui Paulo Martins (ISSCC, 2016)

A Time-Interleaved Ring-VCO with Reduced 1/f3 Phase Noise Corner, Extended Tuning Range and Inherent Divided Output. - Jun Yin 001; Pui-In Mak; Franco Maloberti; Rui Paulo Martins (IEEE J. Solid State Circuits, 2016)

A 0.05- to 10-GHz, 19- to 22-GHz, and 38- to 44-GHz Frequency Synthesizer for Software-Defined Radios in 0.13-µm CMOS Process. - Sujiang Rong; Jun Yin 001; Howard C. Luong (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

24.4 A 0.18V 382µW bluetooth low-energy (BLE) receiver with 1.33nW sleep power for energy-harvesting applications in 28nm CMOS. - Wei-Han Yu; Haidong Yi; Pui-In Mak; Jun Yin 001; Rui Paulo Martins (ISSCC, 2017)

A 2.4-GHz ZigBee Transmitter Using a Function-Reuse Class-F DCO-PA and an ADPLL Achieving 22.6% (14.5%) System Efficiency at 6-dBm (0-dBm) Pout. - Xingqiang Peng; Jun Yin 001; Pui-In Mak; Wei-Han Yu; Rui Paulo Martins (IEEE J. Solid State Circuits, 2017)

A 2.4-GHz Single-Pin Antenna Interface RF Front-End with a Function-Reuse Single-MOS VCO-PA and a Push-Pull LNA. - Kai Xu; Jun Yin 001; Pui-In Mak; Robert Bogdan Staszewski; Rui Paulo Martins (A-SSCC, 2018)

An inverse-class-F CMOS VCO with intrinsic-high-Q 1st- and 2nd-harmonic resonances for 1/f2-to-1/f3 phase-noise suppression achieving 196.2dBc/Hz FOM. - Chee-Cheow Lim; Jun Yin 001; Pui-In Mak; Harikrishnan Ramiah; Rui Paulo Martins (ISSCC, 2018)

A 0.0056mm2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and -249dB FOM. - Shiheng Yang; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (ISSCC, 2018)

A 0.2V energy-harvesting BLE transmitter with a micropower manager achieving 25% system efficiency at 0dBm output and 5.2nW sleep power in 28nm CMOS. - Jun Yin 001; Shiheng Yang; Haidong Yi; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (ISSCC, 2018)

Design and Optimization of a Class-C/D VCO for Ultra-Low-Power IoT and Cellular Applications. - Ricardo Martins 003; Nuno Lourenço 003; Nuno Horta; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (SMACD, 2018)

An Inverse-Class-F CMOS Oscillator With Intrinsic-High-Q First Harmonic and Second Harmonic Resonances. - Chee-Cheow Lim; Harikrishnan Ramiah; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2018)

Low-Phase-Noise Wideband Mode-Switching Quad-Core-Coupled mm-wave VCO Using a Single-Center-Tapped Switched Inductor. - Yatao Peng; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2018)

A 0.18-V 382-µW Bluetooth Low-Energy Receiver Front-End With 1.33-nW Sleep Power for Energy-Harvesting Applications in 28-nm CMOS. - Haidong Yi; Wei-Han Yu; Pui-In Mak; Jun Yin 001; Rui Paulo Martins (IEEE J. Solid State Circuits, 2018)

A Coin-Battery-Powered LDO-Free 2.4-GHz Bluetooth Low-Energy Transmitter With 34.7% Peak System Efficiency. - Xingqiang Peng; Jun Yin 001; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 0.032-mm2 0.15-V Three-Stage Charge-Pump Scheme Using a Differential Bootstrapped Ring-VCO for Energy-Harvesting Applications. - Haidong Yi; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Magnetic-Tuning Millimeter-Wave CMOS Oscillators (Invited Paper). - Xiaolong Liu; Zhiqiang Huang; Jun Yin 001; Howard C. Luong (CICC, 2019)

Using EDA Tools to Push the Performance Boundaries of an Ultralow-Power IoT-VCO at 65nm. - Ricardo Martins 003; Nuno Lourenço 003; Nuno Horta; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (SMACD, 2019)

A coin-battery-powered LDO-Free 2.4-GHz Bluetooth Low Energy/ZigBee receiver consuming 2 mA. - Zechariah Balan; Harikrishnan Ramiah; Jagadheswaran Rajendran; Nandini Vitee; Pravinah Nair Shasidharan; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (Integr., 2019)

A 0.0056-mm2 -249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs. - Shiheng Yang; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2019)

A 0.2-V Energy-Harvesting BLE Transmitter With a Micropower Manager Achieving 25% System Efficiency at 0-dBm Output and 5.2-nW Sleep Power in 28-nm CMOS. - Shiheng Yang; Jun Yin 001; Haidong Yi; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2019)

CMOS Cross-Coupled Differential-Drive Rectifier in Subthreshold Operation for Ambient RF Energy Harvesting - Model and Analysis. - Gabriel Chong; Harikrishnan Ramiah; Jun Yin 001; Jagadheswaran Rajendran; Wei Ru Wong; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 0.5-V 0.4-to-1.6-GHz 8-Phase Bootstrap Ring-VCO Using Inherent Non-Overlapping Clocks Achieving a 162.2-dBc/Hz FoM. - Tongquan Jiang; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 5.1-to-7.3 mW, 2.4-to-5 GHz Class-C Mode-Switching Single-Ended-Complementary VCO Achieving >190 dBc/Hz FoM. - Chee-Cheow Lim; Harikrishnan Ramiah; Jun Yin 001; Narendra Kumar 001; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A Comparative Study of 8-Phase Feedforward-Coupling Ring VCOs. - Iat-Fai Sun; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N Bang-Bang Digital PLL With 8-µs Settling Time for Multi-ISM-Band ULP Radios. - Ka-Fai Un; Gengzhen Qi; Jun Yin 001; Shiheng Yang; Shupeng Yu; Chio-In Ieong; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow-Phase-Noise Cellular Applications. - Ricardo Martins 003; Nuno Lourenço 003; Nuno Horta; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2019)

17.9 A 9mW 54.9-to-63.5GHz Current-Reuse LO Generator with a 186.7dBc/Hz FoM by Unifying a 20GHz 3rd-Harmonic-Rich Current-Output VCO, a Harmonic-Current Filter and a 60GHz TIA. - Chao Fan; Jun Yin 001; Chee-Cheow Lim; Pui-In Mak; Rui Paulo Martins (ISSCC, 2020)

10.1 A 1.4-to-2.7GHz FDD SAW-Less Transmitter for 5G-NR Using a BW-Extended N-Path Filter-Modulator, an Isolated-BB Input and a Wideband TIA-Based PA Driver Achieving <-157.5dBc/Hz OB Noise. - Gengzhen Qi; Haijun Shao; Pui-In Mak; Jun Yin 001; Rui Paulo Martins (ISSCC, 2020)

A Multiband FDD SAW-Less Transmitter for 5G-NR Featuring a BW-Extended N-Path Filter-Modulator, a Switched-BB Input, and a Wideband TIA-Based PA Driver. - Gengzhen Qi; Haijun Shao; Pui-In Mak; Jun Yin 001; Rui Paulo Martins (IEEE J. Solid State Circuits, 2020)

A Single-Pin Antenna Interface RF Front End Using a Single-MOS DCO-PA and a Push-Pull LNA. - Kai Xu; Jun Yin 001; Pui-In Mak; Robert Bogdan Staszewski; Rui Paulo Martins (IEEE J. Solid State Circuits, 2020)

Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA Tools. - Ricardo Martins 003; Nuno Lourenço 003; Nuno Horta; Shenke Zhong; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst., 2020)

A 3.15-mW +16.0-dBm IIP3 22-dB CG Inductively Source Degenerated Balun-LNA Mixer With Integrated Transformer-Based Gate Inductor and IM2 Injection Technique. - Nandini Vitee; Harikrishnan Ramiah; Pui-In Mak; Jun Yin 001; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A 1-V 4-mW Differential-Folded Mixer With Common-Gate Transconductor Using Multiple Feedback Achieving 18.4-dB Conversion Gain, +12.5-dBm IIP3, and 8.5-dB NF. - Nandini Vitee; Harikrishnan Ramiah; Pui-In Mak; Jun Yin 001; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A 15.2-to-18.2GHz Balanced Dual-Core Inverse-Class-F VCO with Q-Enhanced 2nd-Harmonic Resonance Achieving 187-to-188.1dBc/Hz FoM in 28nm CMOS. - Xi Meng; Junqi Guo; Haoran Li; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (A-SSCC, 2021)

A Periodically Time-Varying Inductor Applied to The Class-D VCO for Phase Noise Improvement. - Jun Yin 001; Pui-In Mak; Rui Paulo Martins (ESSCIRC, 2021)

Bird's-eye view of analog and mixed-signal chips for the 21st century. - Rui Paulo Martins; Pui-In Mak; Chi-Hang Chan; Jun Yin 001; Yan Zhu 001; Yong Chen 005; Yan Lu 002; Man-Kay Law; Sai-Weng Sin (Int. J. Circuit Theory Appl., 2021)

A Wide-PCE-Dynamic-Range CMOS Cross-Coupled Differential-Drive Rectifier for Ambient RF Energy Harvesting. - Gabriel Chong; Harikrishnan Ramiah; Jun Yin 001; Jagadheswaran Rajendran; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

An 800 MHz-to-3.3 GHz 20-MHz Channel Bandwidth WPD CMOS Power Amplifier For Multiband Uplink Radio Transceivers. - Selvakumar Mariappan; Jagadheswaran Rajendran; Harikrishnan Ramiah; Pui-In Mak; Jun Yin 001; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS. - Shiheng Yang; Jun Yin 001; Tailong Xu; Taimo Yi; Pui-In Mak; Qiang Li 021; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS. - Peng Chen 022; Xi Meng; Jun Yin 001; Pui-In Mak; Rui Paulo Martins; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS. - Peng Chen 022; Jun Yin 001; Feifei Zhang; Pui-In Mak; Rui Paulo Martins; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop. - Yueduo Liu; Rongxin Bao; Zihao Zhu; Shiheng Yang; Xiong Zhou; Jun Yin 001; Pui-In Mak; Qiang Li 021 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 6-to-7.5-GHz 54-fsrms Jitter Type-II Reference-Sampling PLL Featuring a Gain-Boosting Phase Detector for In-Band Phase-Noise Reduction. - Tailong Xu; Shenke Zhong; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 13.5-to-28.8GHz 72.3%-Locking Range Multi-Phase Injection-Locked Frequency Tripler with Improved Output Power and Wideband Subharmonic-Spur Rejection in 28nm CMOS. - Chao Fan; Ya Zhao; Yanlong Zhang; Jun Yin 001; Pui-In Mak; Guohe Zhang; Li Geng (CICC, 2023)

A ULP Long-Range Active-RF Tag with Automatic Antenna-Interface Calibration Achieving 20.5% TX Efficiency at -22dBm EIRP, and -60.4dBm Sensitivity at 17.8nW RX Power. - Zhizhan Yang; Jun Yin 001; Wei-Han Yu; Haochen Zhang; Pui-In Mak; Rui Paulo Martins (ISSCC, 2023)

A 22.4-to-26.8GHz Dual-Path-Synchronized Quad-Core Oscillator Achieving -138dBc/Hz PN and 193.3dBc/Hz FoM at 10MHz Offset from 25.8GHz. - Xiangxun Zhan; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (ISSCC, 2023)

On the DC-Settling Process of the Pierce Crystal Oscillator in Start-Up. - Zehao Zhang; Shiheng Yang; Yueduo Liu; Zihao Zhu; Jiahui Lin; Rongxin Bao; Tailong Xu; Zhizhan Yang; Mingkang Zhang; Jiaxin Liu; Xiong Zhou; Jun Yin 001; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 3.57-mW 2.88-GHz Multi-Phase Injection-Locked Ring-VCO With a 200-kHz 1/f³ Phase Noise Corner. - Chao Fan; Ya Zhao; Yanlong Zhang; Jun Yin 001; Li Geng; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 0.0043-mm2 0.085-μW/MHz Relaxation Oscillator Using Charge-Prestored Asymmetric Swings R-RC Network. - Yuchen Wei; Shiheng Yang; Yueduo Liu; Rongxin Bao; Zihao Zhu; Jiahui Lin; Zehao Zhang; Yong Chen 005; Jun Yin 001; Pui-In Mak; Qiang Li 021 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Analysis and Design of a 15.2-to-18.2-GHz Inverse-Class-F VCO With a Balanced Dual-Core Topology Suppressing the Flicker Noise Upconversion. - Xi Meng; Haoran Li; Peng Chen 022; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 6.0-to-6.9GHz 99fsrms-Jitter Type-II Sampling PLL with Automatic Frequency and Phase Calibration Method Achieving 0.62μs Locking Time in 28nm CMOS. - Jian Yang; Tailong Xu; Xi Meng; Zhenghao Li; Jun Yin 001; Pui-In Mak; Rui Paulo Martins; Quan Pan 002 (CICC, 2024)

An FVF-LDO with Differential EA and Push-Pull Super Source Follower for Fast Transient Response. - Ruiyuan Chen; Xiangyu Mao; Jun Yin 001; Yan Lu 002 (ICTA, 2024)

A Wide-Load-Range High-PSR Capless Low-Dropout Regulator with Adaptive Supply-Ripple Cancellation. - Linzhi Xie; Xiangyu Mao; Jun Yin 001; Yan Lu 002 (ICTA, 2024)

10.9 A 23.2-to-26GHz Sub-Sampling PLL Achieving 48.3fsrms Jitter, -253.5dB FoMJ, and 0.55μs Locking Time Based on a Function-Reused VCO-Buffer and a Type-I FLL with Rapid Phase Alignment. - Haoran Li; Tailong Xu; Xi Meng; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (ISSCC, 2024)

19.4 A 0.07 mm2 20-to-23.8GHz 8-phase Oscillator Incorporating Magnetic + Dual-Injection Coupling Achieving 189.2dBc/Hz FoM@10 MHz and 200.7dBc/Hz FoMA in 65nm CMOS. - Ya Zhao; Chao Fan; Qiuyu Fang; Guohe Zhang; Jun Yin 001; Pui-In Mak; Li Geng (ISSCC, 2024)

A 5.6-dB Noise Figure, 63-86-GHz Receiver Using a Wideband Noise-Cancelling Low Noise Amplifier With Phase and Amplitude Compensation. - Changxuan Han; Zhixian Deng; Yiyang Shu; Jun Yin 001; Pui-In Mak; Xun Luo (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A Radio-Frequency Cross-Connected Rectifier With LC Source Degeneration. - Qiujin Chen; Mo Huang; Tian Xia; Jun Yin 001; Haiwen Liu; Rui Paulo Martins; Yan Lu 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A Compact Sub-nW/kHz Relaxation Oscillator Using a Negative-Offset Comparator With Chopping and Piecewise Charge-Acceleration in 28-nm CMOS. - Yueduo Liu; Zihao Zhu; Rongxin Bao; Jiahui Lin; Jun Yin 001; Qiang Li 021; Pui-In Mak; Shiheng Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 12.9-to-24 GHz Dual-Mode Multi-Coil VCO Achieving 199.2 dBc/Hz Peak FoMT in 65-nm CMOS. - Ya Zhao; Chao Fan; Yuanxing Peng; Chenglong Liang; Jun Yin 001; Pui-In Mak; Li Geng (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Analysis and Design of a 21.2-to-25.5-GHz Triple-Coil Transformer-Coupled QVCO. - Ya Zhao; Chao Fan; Jun Yin 001; Pui-In Mak; Li Geng (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A Complementary Drain-Grounded VCO-PA Improving Transmit Efficiency Over a Wide EIRP Range. - Zhizhan Yang; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A ULP Long-Range Active-RF Tag With Automatically Calibrated Antenna-TRX Interface. - Zhizhan Yang; Jun Yin 001; Wei-Han Yu; Haochen Zhang; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

A 23.2-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reused VCO-Buffer and a Type-I FLL With Rapid Phase Alignment. - Haoran Li; Tailong Xu; Xi Meng; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

A High Bandwidth Capacitorless NMOS LDO with Pole-Tracking Scheme and Adaptive FFRC Achieving -65dB PSR across Full Load Range. - Jinshuo Xu; Xiaoyan Zhao; Xiangyu Mao; Jun Yin 001; Mo Huang; Yan Lu 002 (ISCAS, 2025)

A 0.6V Digital-intensive Pulse Injection 32-kHz Crystal Oscillator Using Stacked Logic Gates. - Zhizhan Yang; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (ISCAS, 2025)

19.7 A 27GHz Fractional-N Sub-Sampling PLL Achieving 57.9fsrms Jitter, -249.7dB FoM, and 1.98µS Locking Time Using Polarity-Reversible SSPD. - Haoran Li; Jinge Li; Xueying Jiang; Xi Meng; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (ISSCC, 2025)

A 0.4μW/MHz Reference-Replication-Based RC Oscillator with Path-Delay and Comparator-Offset Cancellation Achieving 9.83ppm/°C from -40 to 125°C. - Yueduo Liu; Zihao Zhu; Xinyu Yang; Rongxin Bao; Zehao Zhang; Hongshuai Zhang; Jiaxin Liu; Zheng Wang; Mingkang Zhang; Na Yan; Jun Yin 001; Pui-In Mak; et al. (ISSCC, 2025)

A 94.8nW Battery-Free Intelligent Silicon Platform Enabling Distributed, Adaptive, and Event-Driven Multimodal Sensing at the Edge. - Haochen Zhang; Wei-Han Yu; Zhongyu Zhao; Zhizhan Yang; Ka-Fai Un; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (ISSCC, 2025)

A 90.7-nW Vibration-Based Condition Monitoring Chip Featuring a Digital Compute-in-Memory- Based DNN Accelerator Using an Ultra-Low-Power 13T-SRAM Cell. - Haochen Zhang; Wei-Han Yu; Zhizhan Yang; Ka-Fai Un; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2025)

A Series-LC-Assisted Oscillator Achieving -140.2 dBc/Hz Phase Noise and 187.5 dBc/Hz FoM at 10 MHz Offset From 10.7 GHz. - Xiangxun Zhan; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

An 840-to-970 MHz Multimodal Wake-Up Receiver With a Q-Equalized Antenna-ED Interface and 2-Dimensional Wake-Up Identification. - Zhizhan Yang; Haochen Zhang; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction. - Tailong Xu; Haoran Li; Xi Meng; Xiangxun Zhan; Yatao Peng; Jun Yin 001; Shiheng Yang; Chao Fan; Zhixiang Huang; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A Systematic Review of Voltage Reference Circuits: Spanning Room Temperature to Cryogenic Applications. - Chen Deng; Sai Wu; Chengcheng Liu; Yatao Peng; Man-Kay Law; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A 0.0019-mm² LC-Ring Oscillator With an Ultra-Compact Transformer Achieving 175.2 dBc/Hz FoM@1MHz and 202.4 dBc/Hz FoMA. - Ya Zhao; Lingao Huang; Runchen Wang; Jun Yin 001; Pui-In Mak; Li Geng; Chao Fan (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

Analyses Concerning the Phase Noise and Nonlinear Behavior of the Charge-Sharing Integrator-Based Hybrid PLL. - Jingrun Song; Xinyu Yang; Jiaxu Liu; Yueduo Liu; Zihao Zhu; Zhengxuan Han; Zehao Zhang; Jiaxin Liu; Hongshuai Zhang; Jun Yin 001; Pui-In Mak; Shiheng Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

Design and Analysis of a Type-II Sampling PLL With Automatic Frequency and Phase Calibrations Achieving 0.62-μs Locking Time. - Jian Yang; Tailong Xu; Xi Meng; Zhenghao Li; Jun Yin 001; Rui Paulo Martins; Pui-In Mak; Quan Pan 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)