A Chosen - Plaintext Differential Power Analysis Attack on HMAC - SM3. - Limin Guo; Lihui Wang; Dan Liu; Weijun Shan; Zhimin Zhang; Qing Li 064; Jun Yu 010 (CIS, 2015)

Differential Power Analysis on Dynamic Password Token Based on SM3 Algorithm, and Countermeasures. - Limin Guo; Lihui Wang; Qing Li 064; Jun Yu 010; Peng Luo (CIS, 2015)

A New SPA Attack on ECC with Regular Point Multiplication. - Lihui Wang; Qing Li 064; Gang Zhang; Jun Yu 010; Zhimin Zhang; Limin Guo; David Wei Zhang (CIS, 2015)

A Survey on Energy Internet: Architecture, Approach, and Emerging Technologies. - Kun Wang 005; Jun Yu 010; Yan Yu; Yirou Qian; Deze Zeng; Song Guo 001; Yong Xiang 001; Jinsong Wu 001 (IEEE Syst. J., 2018)

A Horizontal Attack on SM9 Signature Generation. - Weijun Shan; Jun Yu 010; Limin Guo; Kun Jiang 004; Lihui Wang; Qing Li 064 (CIS, 2019)

Analytical Placement with 3D Poisson's Equation and ADMM Based Optimization for Large-Scale 2.5D Heterogeneous FPGAs. - Jianli Chen; Wenxing Zhu; Jun Yu 010; Lei He 001; Yao-Wen Chang (ICCAD, 2019)

Timing-Aware Fill Insertions with Design-Rule and Density Constraints. - Tingshen Lan; Xingquan Li; Jianli Chen; Jun Yu 010; Lei He 001; Senhua Dong; Wenxing Zhu; Yao-Wen Chang (ICCAD, 2019)

Design and verification of universal evaluation system for single event effect sensitivity measurement in very-large-scale integrated circuits. - Liewei Xu; Chang Cai; Tianqi Liu; Lingyun Ke; Jun Yu 010; Chang Wu (IEICE Electron. Express, 2019)

An Efficient EPIST Algorithm for Global Placement with Non-Integer Multiple-Height Cells *. - Jianli Chen; Zhipeng Huang 009; Ye Huang; Wenxing Zhu; Jun Yu 010; Yao-Wen Chang (DAC, 2020)

Late Breaking Results: An Analytical Timing-Driven Placer for Heterogeneous FPGAs*. - Zhifeng Lin; Yanyue Xie; Gang Qian; Sifei Wang; Jun Yu 010; Jianli Chen (DAC, 2020)

Time-Division Multiplexing Based System-Level FPGA Routing for Logic Verification. - Peng Zou; Zhifeng Lin; Xiao Shi; Yingjie Wu; Jianli Chen; Jun Yu 010; Yao-Wen Chang (DAC, 2020)

Simulation of SEU Response of Advanced 20 nm FDSOI SRAMs. - Chang Cai; Luchang Ding; Ze He; Jian Yu; Jie Liu; Jiyuan Bai; Gengsheng Chen; Jun Yu 010 (ASICON, 2021)

CongestNN: An Bi-Directional Congestion Prediction Framework for Large-Scale Heterogeneous FPGAs. - Chenyue Ma; Yifeng Xiao; Sifei Wang; Jun Yu 010; Jianli Chen (ASICON, 2021)

Analytical Global Placement for Heterogenous FPGAs Based on the eDensity Model. - Huimin Wang; Xingyu Tong 001; Runming Shi; Sifei Wang; Jun Yu 010; Jianli Chen (ASICON, 2021)

Late Breaking Results: An Effective Legalization Algorithm for Heterogeneous FPGAs with Complex Constraints. - Zhipeng Huang 009; Haokai Sun; Huimin Wang; Ziran Zhu; Jun Yu 010; Jianli Chen (DAC, 2021)

Late Breaking Results: Novel Discrete Dynamic Filled Function Algorithm for Acyclic Graph Partitioning. - Jianli Chen; Jiarui Chen; Xiao Shi; Lichong Sun; Jun Yu 010 (DAC, 2021)

Low-Cost Lithography Hotspot Detection with Active Entropy Sampling and Model Calibration. - Yifeng Xiao; Miaodi Su; Haoyu Yang; Jianli Chen; Jun Yu 010; Bei Yu 001 (DAC, 2021)

Late Breaking Results: Incremental 3D Global Routing Considering Cell Movement. - Peng Zou; Zhifeng Lin; Chenyue Ma; Jun Yu 010; Jianli Chen (DAC, 2021)

Timing-Driven Placement for FPGAs with Heterogeneous Architectures and Clock Constraints. - Zhifeng Lin; Yanyue Xie; Gang Qian; Jianli Chen; Sifei Wang; Jun Yu 010; Yao-Wen Chang (DATE, 2021)

Voronoi Diagram Based Heterogeneous Circuit Layout Centerline Extraction for Mask Verification. - Xiqiong Bai; Ziran Zhu; Peng Zou; Jianli Chen; Jun Yu 010; Yao-Wen Chang (ASP-DAC, 2022)

CNN-inspired analytical global placement for large-scale heterogeneous FPGAs. - Huimin Wang; Xingyu Tong 001; Chenyue Ma; Runming Shi; Jianli Chen; Kun Wang 005; Jun Yu 010; Yao-Wen Chang (DAC, 2022)

Biological Activity Prediction of GPCR-targeting Ligands on Heterogeneous FPGA-based Accelerators. - Ruiqi Chen 001; Yuhanxiao Ma; Shaodong Zheng; Shizhen Huang; Chao Chen 042; Jun Yu 010; Kun Wang 005 (FCCM, 2022)

Implementation of Radiation Hardened Flip-Flops Based on Novel Fishbone Layouts. - Chang Cai; Zehao Wu; Jing Zhang; Luchang Ding; Lei Shen; Jun Yu 010; Yaqing Chi (ISCAS, 2022)

Characterization of Single Event Upsets of Nanoscale FDSOI Circuits Based on the Simulation and Irradiation Results. - Luchang Ding; Chang Cai; Gengsheng Chen; Zehao Wu; Jing Zhang; Chang Wu; Jun Yu 010 (ISCAS, 2022)

Timing-Aware Fill Insertions With Design-Rule and Density Constraints. - Xiqiong Bai; Ziran Zhu; Pingping Li; Jianli Chen; Tingshen Lan; Xingquan Li; Jun Yu 010; Wenxing Zhu; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

An Incremental Placement Flow for Advanced FPGAs With Timing Awareness. - Zhifeng Lin; Yanyue Xie; Peng Zou; Sifei Wang; Jun Yu 010; Jianli Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

PUFFER: A Routability-Driven Placement Framework via Cell Padding with Multiple Features and Strategy Exploration. - Zhijie Cai; Peng Zou; Zhengtao Wu; Xingyu Tong 001; Jun Yu 010; Jianli Chen; Yao-Wen Chang (DAC, 2023)

Mixed-cell-height Placement with Minimum-Implant-Area and Drain-to-Drain Abutment Constraints. - Guohao Chen 001; Zheng Zeng; Benchao Zhu; Jiawei Li; Kun Wang 005; Jun Yu 010; Jianli Chen (DAC, 2023)

Toward Optimal Filler Cell Insertion with Complex Implant Layer Constraints. - Peng Zou; Guohao Chen 001; Zhifeng Lin; Jun Yu 010; Jianli Chen (DAC, 2023)

Transformer-OPU: An FPGA-based Overlay Processor for Transformer Networks. - Yueyin Bai; Hao Zhou 008; Keqing Zhao; Jianli Chen; Jun Yu 010; Kun Wang 005 (FCCM, 2023)

Moth: A Hardware Accelerator for Neural Radiance Field Inference on FPGA. - Yuanfang Wang; Yu Li 003; Haoyang Zhang; Jun Yu 010; Kun Wang 005 (FCCM, 2023)

Graph-OPU: An FPGA-Based Overlay Processor for Graph Neural Networks. - Ruiqi Chen 001; Haoyang Zhang; Yuhanxiao Ma; Enhao Tang; Shun Li; Yanxiang Zhu; Jun Yu 010; Kun Wang 005 (FPGA, 2023)

LTrans-OPU: A Low-Latency FPGA-Based Overlay Processor for Transformer Networks. - Yueyin Bai; Hao Zhou 008; Keqing Zhao; Manting Zhang; Jianli Chen; Jun Yu 010; Kun Wang 005 (FPL, 2023)

Graph-OPU: A Highly Integrated FPGA-Based Overlay Processor for Graph Neural Networks. - Ruiqi Chen 001; Haoyang Zhang; Shun Li; Enhao Tang; Jun Yu 010; Kun Wang 005 (FPL, 2023)

FPGA Accelerating Multi-Source Transfer Learning with GAT for Bioactivities of Ligands Targeting Orphan G Protein-Coupled Receptors. - Ruiqi Chen 001; Haoyang Zhang; Jun Yu 010; Kun Wang 005 (FPL, 2023)

DIF-LUT: A Simple Yet Scalable Approximation for Non-Linear Activation Function on FPGA. - Yang Liu 376; Xiaoming He; Jun Yu 010; Kun Wang 005 (FPL, 2023)

g-BERT: Enabling Green BERT Deployment on FPGA via Hardware-Aware Hybrid Pruning. - Yueyin Bai; Hao Zhou 008; Ruiqi Chen 001; Kuangjie Zou; Jialin Cao; Haoyang Zhang; Jianli Chen; Jun Yu 010; Kun Wang 005 (ICC, 2023)

FET-OPU: A Flexible and Efficient FPGA-Based Overlay Processor for Transformer Networks. - Yueyin Bai; Hao Zhou 008; Keqing Zhao; Hongji Wang; Jianli Chen; Jun Yu 010; Kun Wang 005 (ICCAD, 2023)

PP-Transformer: Enable Efficient Deployment of Transformers Through Pattern Pruning. - Jialin Cao; Xuanda Lin; Manting Zhang; Kejia Shi; Jun Yu 010; Kun Wang 005 (ICCAD, 2023)

Edge FPGA-based Onsite Neural Network Training. - Ruiqi Chen 001; Haoyang Zhang; Yu Li 003; Runzhou Zhang; Guoyu Li; Jun Yu 010; Kun Wang 005 (ISCAS, 2023)

eSSpMV: An Embedded-FPGA-based Hardware Accelerator for Symmetric Sparse Matrix-Vector Multiplication. - Ruiqi Chen 001; Haoyang Zhang; Yuhanxiao Ma; Jianli Chen; Jun Yu 010; Kun Wang 005 (ISCAS, 2023)

Access Your Tesla without Your Awareness: Compromising Keyless Entry System of Model 3. - Xinyi Xie; Kun Jiang 004; Rui Dai; Jun Lu; Lihui Wang; Qing Li 064; Jun Yu 010 (NDSS, 2023)

Incremental 3-D Global Routing Considering Cell Movement and Complex Routing Constraints. - Peng Zou; Zhijie Cai; Zhifeng Lin; Chenyue Ma; Jun Yu 010; Jianli Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Analytical Placement with 3D Poisson's Equation and ADMM-based Optimization for Large-scale 2.5D Heterogeneous FPGAs. - Min Wei; Xingyu Tong 001; Yuan Wen; Jianli Chen; Jun Yu 010; Wenxing Zhu; Yao-Wen Chang (ACM Trans. Design Autom. Electr. Syst., 2023)

Booth-NeRF: An FPGA Accelerator for Instant-NGP Inference with Novel Booth-Multiplier. - Zihang Ma; Zeyu Li; Yuanfang Wang; Yu Li 003; Jun Yu 010; Kun Wang 005 (ASPDAC, 2024)

TransFRU: Efficient Deployment of Transformers on FPGA with Full Resource Utilization. - Hongji Wang; Yueyin Bai; Jun Yu 010; Kun Wang 005 (ASPDAC, 2024)

CSTrans-OPU: An FPGA-based Overlay Processor with Full Compilation for Transformer Networks via Sparsity Exploration. - Yueyin Bai; Keqing Zhao; Yang Liu 376; Hongji Wang; Hao Zhou 008; Xiaoxing Wu; Jun Yu 010; Kun Wang 005 (DAC, 2024)

FLAME: Fully Leveraging MoE Sparsity for Transformer on FPGA. - Xuanda Lin; Huinan Tian; Wenxiao Xue; Lanqi Ma; Jialin Cao; Manting Zhang; Jun Yu 010; Kun Wang 005 (DAC, 2024)

FNM-Trans: Efficient FPGA-based Transformer Architecture with Full N: M Sparsity. - Manting Zhang; Jialin Cao; Kejia Shi; Keqing Zhao; Genhao Zhang; Jun Yu 010; Kun Wang 005 (DAC, 2024)

Fitop-Trans: Maximizing Transformer Pipeline Efficiency through Fixed-Length Token Pruning on FPGA. - Kejia Shi; Manting Zhang; Keqing Zhao; Xiaoxing Wu; Yang Liu 376; Jun Yu 010; Kun Wang 005 (FPL, 2024)

FLOP: A Flexible Memory-Optimized Processor for Parallel Graph Mining on FPGA. - Guoyu Li; Runzhou Zhang; Jun Yu 010; Kun Wang 005 (ICCAD, 2024)

TransLib: An Extensible Graph-Aware Library Framework for Automated Generation of Transformer Operators on FPGA. - Yang Liu 376; Tianchen Wang; Yuxuan Dong; Zexu Zhang; Shun Li; Jun Yu 010; Kun Wang 005 (ICCAD, 2024)

FAS-Trans: Fully Exploiting FFN and Attention Sparsity for Transformer on FPGA. - Hongji Wang; Kun Wang 005; Yifan Zhang; Jun Yu 010 (ICCAD, 2024)

Edge-BiT: Software-Hardware Co-design for Optimizing Binarized Transformer Networks Inference on Edge FPGA. - Shuai Zhou; Sisi Meng; Huinan Tian; Jun Yu 010; Kun Wang 005 (ICCAD, 2024)

Graph-OPU: A Highly Flexible FPGA-Based Overlay Processor for Graph Neural Networks. - Enhao Tang; Shun Li; Ruiqi Chen 001; Hao Zhou 008; Yuhanxiao Ma; Haoyang Zhang; Jun Yu 010; Kun Wang 005 (ACM Trans. Reconfigurable Technol. Syst., 2024)

Trojan Insertion versus Layout Defenses for Modern ICs: Red-versus-Blue Teaming in a Competitive Community Effort. - Johann Knechtel; Mohammad Eslami; Peng Zou; Min Wei; Xingyu Tong 001; Binggang Qiu; Zhijie Cai; Guohao Chen 001; Benchao Zhu; Jiawei Li; Jun Yu 010; Jianli Chen; et al. (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2025)