Commercial Design Verification: Methodology and Tools. - Carl Pixley; Noel R. Strader; William C. Bruce; Jaehong Park; Matt Kaufmann; Kurt Shultz; Michael Burns; Jainendra Kumar; Jun Yuan 007; Janet Nguyen (ITC, 1996)

On Combining Formal and Informal Verification. - Jun Yuan 007; Jian Shen; Jacob A. Abraham; Adnan Aziz (CAV, 1997)

Approximate reachability don't cares for CTL model checking. - In-Ho Moon; Jae-Young Jang; Gary D. Hachtel; Fabio Somenzi; Jun Yuan 007; Carl Pixley (ICCAD, 1998)

Modeling design constraints and biasing in simulation using BDDs. - Jun Yuan 007; Kurt Shultz; Carl Pixley; Hillel Miller; Adnan Aziz (ICCAD, 1999)

Integrated Formal and Informal Design Verification of Commercial Integrated Circuits. - Carl Pixley; Kurt Shultz; Jun Yuan 007 (PDPTA, 1999)

Automatic Vector Generation Using Constraints and Biasing. - Jun Yuan 007; Kurt Shultz; Carl Pixley; Hillel Miller; Adnan Aziz (J. Electron. Test., 2000)

Efficient control state-space search. - Adnan Aziz; James H. Kukula; Thomas R. Shiple; Jun Yuan 007 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Simplifying Constraint Solving in Random Simulation Generation. - Jun Yuan 007; Ken Albin; Adnan Aziz; Carl Pixley (IWLS, 2002)

A Method for Synthesizing Boolean Constrains. - Jun Yuan 007; Kurt Shultz; John Havlicek; Ken Albin; Adnan Aziz (IWLS, 2002)

Constraint synthesis for environment modeling in functional verification. - Jun Yuan 007; Ken Albin; Adnan Aziz; Carl Pixley (DAC, 2003)

A Framework for Constrained Functional Verification. - Jun Yuan 007; Carl Pixley; Adnan Aziz; Ken Albin (ICCAD, 2003)

Simplifying Boolean constraint solving for random simulation-vector generation. - Jun Yuan 007; Adnan Aziz; Carl Pixley; Ken Albin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Constraint-based verification. - Jun Yuan 007; Carl Pixley; Adnan Aziz (Springer, 2006)