Design and implementation of an embedded 512KB level 2 cache subsystem. - Jinuk Luke Shin; Bruce Petrick; Howard Levy; Jinseung Son; Mandeep Singh; Vikas Mathur; Jung-Cheng Yeh; Heesung Choi; Vishal Gupta; Tom Ziaja; Ana Sonia Leon (CICC, 2004)

A 2GHz, 7W (max) 64b PowerTM Microprocessor Core. - Daniel Murray; James Burnette; Brian Campbell 004; Mark Chung; Bruce Fernandes; Subhendra Ghosh; Rajat Goel; Greg Hess; Hang Huang; Zhibin Huang; Naveen Javarappa; Pradeep Kanapathipillai; et al. (CICC, 2007)