An all-digital delay-locked loop for high-speed memory interface applications. - Shih-Lun Chen; Ming-Jing Ho; Yu-Ming Sun; Maung Wai Lin; Jung-Chin Lai (VLSI-DAT, 2014)

Mismatch-tolerant time amplifier with embedded self-calibration. - Jung-Chin Lai; Terng-Yin Hsu (ICCE-Berlin, 2015)

The calibration of gain error for time amplifier embedded in time-to-digital converter. - Jung-Chin Lai; Frank Hsiao (DSC, 2017)

Cost-Effective Time-to-Digital Converter Using Time-Residue Feedback. - Jung-Chin Lai; Terng-Yin Hsu (IEEE Trans. Ind. Electron., 2017)

All-Digital Mismatched Calibrator and Compensator for SR Latch-Based Variable-Gain Time Amplifier. - Kuan-Chieh Chao; Jung-Chin Lai; Terng-Yin Hsu (IEEE Access, 2020)