Merrimac: Supercomputing with Streams. - William J. Dally; Francois Labonte; Abhishek Das; Pat Hanrahan; Jung Ho Ahn; Jayanth Gummaraju; Mattan Erez; Nuwan Jayasena; Ian Buck; Timothy J. Knight; Ujval J. Kapasi (SC, 2003)

Programmable Stream Processors. - Ujval J. Kapasi; Scott Rixner; William J. Dally; Brucek Khailany; Jung Ho Ahn; Peter R. Mattson; John D. Owens (Computer, 2003)

Stream Register Files with Indexed Access. - Nuwan Jayasena; Mattan Erez; Jung Ho Ahn; William J. Dally (HPCA, 2004)

Evaluating the Imagine Stream Architecture. - Jung Ho Ahn; William J. Dally; Brucek Khailany; Ujval J. Kapasi; Abhishek Das (ISCA, 2004)

Analysis and Performance Results of a Molecular Modeling Application on Merrimac. - Mattan Erez; Jung Ho Ahn; Ankit Garg; William J. Dally; Eric Darve (SC, 2004)

Stream Processors: Progammability and Efficiency. - William J. Dally; Ujval J. Kapasi; Brucek Khailany; Jung Ho Ahn; Abhishek Das (ACM Queue, 2004)

Scatter-Add in Data Parallel Architectures. - Jung Ho Ahn; Mattan Erez; William J. Dally (HPCA, 2005)

Architecture - The design space of data-parallel memory systems. - Jung Ho Ahn; Mattan Erez; William J. Dally (SC, 2006)

Data parallel address architecture. - Jung Ho Ahn; William J. Dally (IEEE Comput. Archit. Lett., 2006)

Tradeoff between data-, instruction-, and thread-level parallelism in stream processors. - Jung Ho Ahn; Mattan Erez; William J. Dally (ICS, 2007)

Executing irregular scientific applications on stream architectures. - Mattan Erez; Jung Ho Ahn; Jayanth Gummaraju; Mendel Rosenblum; William J. Dally (ICS, 2007)

A Nanophotonic Interconnect for High-Performance Many-Core Computation. - Raymond G. Beausoleil; Jung Ho Ahn; Nathan L. Binkert; Al Davis; David Fattal; Marco Fiorentino; Norman P. Jouppi; Moray McLaren; Charles M. Santori; Robert S. Schreiber; S. M. Spillane; Dana Vantrease; et al. (Hot Interconnects, 2008)

A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies. - Shyamkumar Thoziyoor; Jung Ho Ahn; Matteo Monchiero; Jay B. Brockman; Norman P. Jouppi (ISCA, 2008)

Corona: System Implications of Emerging Nanophotonic Technology. - Dana Vantrease; Robert Schreiber; Matteo Monchiero; Moray McLaren; Norman P. Jouppi; Marco Fiorentino; Al Davis; Nathan L. Binkert; Raymond G. Beausoleil; Jung Ho Ahn (ISCA, 2008)

McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures. - Sheng Li 007; Jung Ho Ahn; Richard D. Strong; Jay B. Brockman; Dean M. Tullsen; Norman P. Jouppi (MICRO, 2009)

HyperX: topology, routing, and packaging of efficient large-scale networks. - Jung Ho Ahn; Nathan L. Binkert; Al Davis; Moray McLaren; Robert S. Schreiber (SC, 2009)

Future scaling of processor-memory interfaces. - Jung Ho Ahn; Norman P. Jouppi; Christos Kozyrakis; Jacob Leverich; Robert S. Schreiber (SC, 2009)

Multicore DIMM: an Energy Efficient Memory Module with Independently Controlled DRAMs. - Jung Ho Ahn; Jacob Leverich; Robert S. Schreiber; Norman P. Jouppi (IEEE Comput. Archit. Lett., 2009)

How to simulate 1000 cores. - Matteo Monchiero; Jung Ho Ahn; Ayose Falcón; Daniel Ortega; Paolo Faraboschi (SIGARCH Comput. Archit. News, 2009)

Replication-aware leakage management in chip multiprocessors with private L2 cache. - Hyunhee Kim; Jung Ho Ahn; Jihong Kim 001 (ISLPED, 2010)

CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study. - Jung Ho Ahn; Raymond G. Beausoleil; Nathan L. Binkert; Al Davis; Marco Fiorentino; Norman P. Jouppi; Moray McLaren; Matteo Monchiero; Naveen Muralimanohar; Robert Schreiber; Dana Vantrease (Low Power Networks-on-Chip, 2011)

Matching cache access behavior and bit error pattern for high performance low Vcc L1 cache. - Young-Geun Choi; Sungjoo Yoo; Sunggu Lee; Jung Ho Ahn (DAC, 2011)

A quantitative analysis of performance benefits of 3D die stacking on mobile and embedded SoC. - Dongki Kim; Sungjoo Yoo; Sunggu Lee; Jung Ho Ahn; Hyunuk Jung (DATE, 2011)

CACTI-P: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques. - Sheng Li 007; Ke Chen 020; Jung Ho Ahn; Jay B. Brockman; Norman P. Jouppi (ICCAD, 2011)

The role of optics in future high radix switch design. - Nathan L. Binkert; Al Davis; Norman P. Jouppi; Moray McLaren; Naveen Muralimanohar; Robert Schreiber; Jung Ho Ahn (ISCA, 2011)

3D network-on-chip with wireless links through inductive coupling. - Jinho Lee; Mingyang Zhu; Kiyoung Choi; Jung Ho Ahn; Rohit Sharma (ISOCC, 2011)

CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory. - Ke Chen 020; Sheng Li 007; Naveen Muralimanohar; Jung Ho Ahn; Jay B. Brockman; Norman P. Jouppi (DATE, 2012)

Network within a network approach to create a scalable high-radix router microarchitecture. - Jung Ho Ahn; Sungwoo Choo; John Kim 001 (HPCA, 2012)

MAGE: adaptive granularity and ECC for resilient and power efficient memory systems. - Sheng Li 007; Doe Hyun Yoon; Ke Chen 020; Jishen Zhao; Jung Ho Ahn; Jay B. Brockman; Yuan Xie 001; Norman P. Jouppi (SC, 2012)

Optical High Radix Switch Design. - Nathan L. Binkert; Al Davis; Norman P. Jouppi; Moray McLaren; Naveen Muralimanohar; Robert Schreiber; Jung Ho Ahn (IEEE Micro, 2012)

Improving System Energy Efficiency with Memory Rank Subsetting. - Jung Ho Ahn; Norman P. Jouppi; Christos Kozyrakis; Jacob Leverich; Robert S. Schreiber (ACM Trans. Archit. Code Optim., 2012)

Memory-centric system interconnect design with Hybrid Memory Cubes. - Gwangsun Kim; John Kim 001; Jung Ho Ahn; Jaeha Kim (PACT, 2013)

Dynamic bandwidth scaling for embedded DSPs with 3D-stacked DRAM and wide I/Os. - Daniel W. Chang; Young Hoon Son; Jung Ho Ahn; Hoyoung Kim; Minwook Ahn; Michael J. Schulte; Nam Sung Kim (ICCAD, 2013)

Reducing memory access latency with asymmetric DRAM bank organizations. - Young Hoon Son; Seongil O; Yuhwan Ro; Jae W. Lee; Jung Ho Ahn (ISCA, 2013)

McSimA+: A manycore simulator with application-level+ simulation and detailed microarchitecture modeling. - Jung Ho Ahn; Sheng Li 007; Seongil O; Norman P. Jouppi (ISPASS, 2013)

Scalable high-radix router microarchitecture using a network switch organization. - Jung Ho Ahn; Young Hoon Son; John Kim 001 (ACM Trans. Archit. Code Optim., 2013)

The McPAT Framework for Multicore and Manycore Architectures: Simultaneously Modeling Power, Area, and Timing. - Sheng Li 007; Jung Ho Ahn; Richard D. Strong; Jay B. Brockman; Dean M. Tullsen; Norman P. Jouppi (ACM Trans. Archit. Code Optim., 2013)

Mapping and Scheduling of Tasks and Communications on Many-Core SoC Under Local Memory Constraint. - Jinho Lee; Moo-Kyoung Chung; Yeon-Gon Cho; Soojung Ryu; Jung Ho Ahn; Kiyoung Choi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

MAEPER: Matching Access and Error Patterns With Error-Free Resource for Low Vcc L1 Cache. - Young-Geun Choi; Sungjoo Yoo; Sunggu Lee; Jung Ho Ahn; Kangmin Lee (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Exploiting Replicated Cache Blocks to Reduce L2 Cache Leakage in CMPs. - Hyunhee Kim; Jung Ho Ahn; Jihong Kim 001 (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Row-buffer decoupling: A case for low-latency DRAM microarchitecture. - Seongil O; Young Hoon Son; Nam Sung Kim; Jung Ho Ahn (ISCA, 2014)

Microbank: Architecting Through-Silicon Interposer-Based Main Memory Systems. - Young Hoon Son; Seongil O; Hyunggyun Yang; Daejin Jung; Jung Ho Ahn; John Kim 001; Jangwoo Kim; Jae W. Lee (SC, 2014)

NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules. - Amin Farmahini Farahani; Jung Ho Ahn; Katherine Morrow; Nam Sung Kim (HPCA, 2015)

CiDRA: A cache-inspired DRAM resilience architecture. - Young Hoon Son; Sukhan Lee 002; Seongil O; Sanghyuk Kwon; Nam Sung Kim; Jung Ho Ahn (HPCA, 2015)

Alloy: Parallel-serial memory channel architecture for single-chip heterogeneous processor systems. - Hao Wang 011; Chang-Jae Park; Gyungsu Byun; Jung Ho Ahn; Nam Sung Kim (HPCA, 2015)

History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures. - Ke Chen 020; Sheng Li 007; Jung Ho Ahn; Naveen Muralimanohar; Jishen Zhao; Cong Xu 002; Seongil O; Yuan Xie 001; Jay B. Brockman; Norman P. Jouppi (ICS, 2015)

Architecting to achieve a billion requests per second throughput on a single key-value store server platform. - Sheng Li 007; Hyeontaek Lim; Victor W. Lee; Jung Ho Ahn; Anuj Kalia; Michael Kaminsky; David G. Andersen; Seongil O; Sukhan Lee 002; Pradeep Dubey (ISCA, 2015)

DRAMA: An Architecture for Accelerated Processing Near Memory. - Amin Farmahini Farahani; Jung Ho Ahn; Katherine Morrow; Nam Sung Kim (IEEE Comput. Archit. Lett., 2015)

CIDR: A Cache Inspired Area-Efficient DRAM Resilience Architecture against Permanent Faults. - Seongil O; Sanghyuk Kwon; Young Hoon Son; Yujin Park; Jung Ho Ahn (IEEE Comput. Archit. Lett., 2015)

Accelerating Linked-list Traversal Through Near-Data Processing. - Byungchul Hong; Gwangsun Kim; Jung Ho Ahn; Yongkee Kwon; Hongsik Kim; John Kim 001 (PACT, 2016)

Buffered compares: Excavating the hidden parallelism inside DRAM architectures with lightweight logic. - Jinho Lee; Jung Ho Ahn; Kiyoung Choi (DATE, 2016)

Adaptive and flexible key-value stores through soft data partitioning. - Byungchul Hong; Yongkee Kwon; Jung Ho Ahn; John Kim 001 (ICCD, 2016)

Chameleon: Versatile and practical near-DRAM acceleration architecture for large memory systems. - Hadi Asghari Moghaddam; Young Hoon Son; Jung Ho Ahn; Nam Sung Kim (MICRO, 2016)

Large Pages on Steroids: Small Ideas to Accelerate Big Memory Applications. - Daejin Jung; Sheng Li 007; Jung Ho Ahn (IEEE Comput. Archit. Lett., 2016)

Exploring new features of high-bandwidth memory for GPUs. - Bingchao Li; Choungki Song; Jizeng Wei; Jung Ho Ahn; Nam Sung Kim (IEICE Electron. Express, 2016)

Achieving One Billion Key-Value Requests per Second on a Single Server. - Sheng Li 007; Hyeontaek Lim; Victor W. Lee; Jung Ho Ahn; Anuj Kalia; Michael Kaminsky; David G. Andersen; Seongil O; Sukhan Lee 002; Pradeep Dubey (IEEE Micro, 2016)

Near-DRAM Acceleration with Single-ISA Heterogeneous Processing in Standard Memory Modules. - Hadi Asghari Moghaddam; Amin Farmahini Farahani; Katherine Morrow; Jung Ho Ahn; Nam Sung Kim (IEEE Micro, 2016)

Full-Stack Architecting to Achieve a Billion-Requests-Per-Second Throughput on a Single Key-Value Store Server Platform. - Sheng Li 007; Hyeontaek Lim; Victor W. Lee; Jung Ho Ahn; Anuj Kalia; Michael Kaminsky; David G. Andersen; Seongil O; Sukhan Lee 002; Pradeep Dubey (ACM Trans. Comput. Syst., 2016)

History-Based Arbitration for Fairness in Processor-Interconnect of NUMA Servers. - WonJun Song; Gwangsun Kim; Hyungjoon Jung; Jongwook Chung; Jung Ho Ahn; Jae W. Lee; John Kim 001 (ASPLOS, 2017)

Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices. - Sang-uhn Cha; Seongil O; Hyunsung Shin; Sangjoon Hwang; Kwang-Il Park; Seong-Jin Jang; Joo-Sun Choi; Gyo-Young Jin; Young Hoon Son; Hyunyoon Cho; Jung Ho Ahn; Nam Sung Kim (HPCA, 2017)

SOUP-N-SALAD: Allocation-Oblivious Access Latency Reduction with Asymmetric DRAM Microarchitectures. - Yuhwan Ro; Hyunyoon Cho; Eojin Lee; Daejin Jung; Young Hoon Son; Jung Ho Ahn; Jae W. Lee (HPCA, 2017)

Work as a team or individual: Characterizing the system-level impacts of main memory partitioning. - Eojin Lee; Jongwook Chung; Daejin Jung; Sukhan Lee 002; Sheng Li 007; Jung Ho Ahn (IISWC, 2017)

Understanding power-performance relationship of energy-efficient modern DRAM devices. - Sukhan Lee 002; Yuhwan Ro; Young Hoon Son; Hyunyoon Cho; Nam Sung Kim; Jung Ho Ahn (IISWC, 2017)

SALAD: Achieving Symmetric Access Latency with Asymmetric DRAM Architecture. - Young Hoon Son; Hyunyoon Cho; Yuhwan Ro; Jae W. Lee; Jung Ho Ahn (IEEE Comput. Archit. Lett., 2017)

Evaluation of Performance Unfairness in NUMA System Architecture. - WonJun Song; Hyungjoon Jung; Jung Ho Ahn; Jae W. Lee; John Kim 001 (IEEE Comput. Archit. Lett., 2017)

Selective DRAM cache bypassing for improving bandwidth on DRAM/NVM hybrid main memory systems. - Yuhwan Ro; Min Chul Sung; Yongjun Park 001; Jung Ho Ahn (IEICE Electron. Express, 2017)

Excavating the Hidden Parallelism Inside DRAM Architectures With Buffered Compares. - Jinho Lee; Jongwook Chung; Jung Ho Ahn; Kiyoung Choi (IEEE Trans. Very Large Scale Integr. Syst., 2017)

3D-Xpath: high-density managed DRAM architecture with cost-effective alternative paths for memory transactions. - Sukhan Lee 002; Kiwon Lee; Min Chul Sung; Mohammad Alian; Chankyung Kim; Wooyeong Cho; Reum Oh; Seongil O; Jung Ho Ahn; Nam Sung Kim (PACT, 2018)

Memory Hierarchy for Web Search. - Grant Ayers; Jung Ho Ahn; Christos Kozyrakis; Parthasarathy Ranganathan (HPCA, 2018)

Leveraging Power-Performance Relationship of Energy-Efficient Modern DRAM Devices. - Sukhan Lee 002; Hyunyoon Cho; Young Hoon Son; Yuhwan Ro; Nam Sung Kim; Jung Ho Ahn (IEEE Access, 2018)

Partitioning Compute Units in CNN Acceleration for Statistical Memory Traffic Shaping. - Daejin Jung; Sunjung Lee; Wonjong Rhee; Jung Ho Ahn (IEEE Comput. Archit. Lett., 2018)

TWiCe: Time Window Counter Based Row Refresh to Prevent Row-Hammering. - Eojin Lee; Sukhan Lee 002; G. Edward Suh; Jung Ho Ahn (IEEE Comput. Archit. Lett., 2018)

Enforcing Last-Level Cache Partitioning through Memory Virtual Channels. - Jongwook Chung; Yuhwan Ro; Joonsung Kim; Jaehyung Ahn; Jangwoo Kim; John Kim 001; Jae W. Lee; Jung Ho Ahn (PACT, 2019)

TWiCe: preventing row-hammering by exploiting time window counters. - Eojin Lee; Ingab Kang; Sukhan Lee 002; G. Edward Suh; Jung Ho Ahn (ISCA, 2019)

Restructuring Batch Normalization to Accelerate CNN Training. - Wonkyung Jung; Daejin Jung; Byeongho Kim; Sunjung Lee; Wonjong Rhee; Jung Ho Ahn (SysML, 2019)

Accelerating Number Theoretic Transformations for Bootstrappable Homomorphic Encryption on GPUs. - Sangpyo Kim; Wonkyung Jung; Jaiyoung Park; Jung Ho Ahn (IISWC, 2020)

Graphene: Strong yet Lightweight Row Hammer Protection. - Yeonhong Park; Woosuk Kwon; Eojin Lee; Tae Jun Ham; Jung Ho Ahn; Jae W. Lee (MICRO, 2020)

CAT-TWO: Counter-Based Adaptive Tree, Time Window Optimized for DRAM Row-Hammer Prevention. - Ingab Kang; Eojin Lee; Jung Ho Ahn (IEEE Access, 2020)

HEAAN Demystified: Accelerating Fully Homomorphic Encryption Through Architecture-centric Analysis and Optimization. - Wonkyung Jung; Eojin Lee; Sangpyo Kim; Keewoo Lee; Namhoon Kim; Chohong Min; Jung Hee Cheon; Jung Ho Ahn (CoRR, 2020)

MViD: Sparse Matrix-Vector Multiplication in Mobile DRAM for Accelerating Recurrent Neural Networks. - Byeongho Kim; Jongwook Chung; Eojin Lee; Wonkyung Jung; Sunjung Lee; Jaewan Choi; Jaehyun Park 006; Minbok Wi; Sukhan Lee 002; Jung Ho Ahn (IEEE Trans. Computers, 2020)

BCD deduplication: effective memory compression using partial cache-line deduplication. - Sungbo Park; Ingab Kang; Yaebin Moon; Jung Ho Ahn; G. Edward Suh (ASPLOS, 2021)

Accelerating Fully Homomorphic Encryption Through Microarchitecture-Aware Analysis and Optimization. - Wonkyung Jung; Eojin Lee; Sangpyo Kim; Namhoon Kim; Keewoo Lee; Chohong Min; Jung Hee Cheon; Jung Ho Ahn (ISPASS, 2021)

MaPHeA: a lightweight memory hierarchy-aware profile-guided heap allocation framework. - Deok-Jae Oh; Yaebin Moon; Eojin Lee; Tae Jun Ham; Yongjun Park 001; Jae W. Lee; Jung Ho Ahn (LCTES, 2021)

TRiM: Enhancing Processor-Memory Interfaces with Scalable Tensor Reduction in Memory. - Jaehyun Park 006; Byeongho Kim; Sungmin Yun 001; Eojin Lee; Minsoo Rhu; Jung Ho Ahn (MICRO, 2021)

Accelerating Fully Homomorphic Encryption Through Architecture-Centric Analysis and Optimization. - Wonkyung Jung; Eojin Lee; Sangpyo Kim; Jongmin Kim 007; Namhoon Kim; Keewoo Lee; Chohong Min; Jung Hee Cheon; Jung Ho Ahn (IEEE Access, 2021)

Row-Streaming Dataflow Using a Chaining Buffer and Systolic Array+ Structure. - Hweesoo Kim; Sunjung Lee; Jaewan Choi; Jung Ho Ahn (IEEE Comput. Archit. Lett., 2021)

TRiM: Tensor Reduction in Memory. - Byeongho Kim; Jaehyun Park 006; Eojin Lee; Minsoo Rhu; Jung Ho Ahn (IEEE Comput. Archit. Lett., 2021)

Over 100x Faster Bootstrapping in Fully Homomorphic Encryption through Memory-centric Optimization with GPUs. - Wonkyung Jung; Sangpyo Kim; Jung Ho Ahn; Jung Hee Cheon; Younho Lee (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021)

Mithril: Cooperative Row Hammer Protection on Commodity DRAM Leveraging Managed Refresh. - Michael Jaemin Kim; Jaehyun Park 006; Yeonhong Park; Wanju Doh; Namhoon Kim; Tae Jun Ham; Jae W. Lee; Jung Ho Ahn (HPCA, 2022)

Accelerating Transformer Networks through Recomposing Softmax Layers. - Jaewan Choi; Hailong Li; Byeongho Kim; Seunghwan Hwang; Jung Ho Ahn (IISWC, 2022)

A Slice and Dice Approach to Accelerate Compound Sparse Attention on GPU. - Hailong Li; Jaewan Choi; Jung Ho Ahn (IISWC, 2022)

BTS: an accelerator for bootstrappable fully homomorphic encryption. - Sangpyo Kim; Jongmin Kim 007; Michael Jaemin Kim; Wonkyung Jung; John Kim 001; Minsoo Rhu; Jung Ho Ahn (ISCA, 2022)

ARK: Fully Homomorphic Encryption Accelerator with Runtime Data Generation and Inter-Operation Key Reuse. - Jongmin Kim 007; Gwangho Lee; Sangpyo Kim; Gina Sohn; Minsoo Rhu; John Kim 001; Jung Ho Ahn (MICRO, 2022)

GraNDe: Near-Data Processing Architecture With Adaptive Matrix Mapping for Graph Convolutional Networks. - Sungmin Yun 001; Byeongho Kim; Jaehyun Park 006; Hwayong Nam; Jung Ho Ahn; Eojin Lee (IEEE Comput. Archit. Lett., 2022)

AESPA: Accuracy Preserving Low-degree Polynomial Activation for Fast Private Inference. - Jaiyoung Park; Michael Jaemin Kim; Wonkyung Jung; Jung Ho Ahn (CoRR, 2022)

Future Scaling of Memory Hierarchy for Tensor Cores and Eliminating Redundant Shared Memory Traffic Using Inter-Warp Multicasting. - Sunjung Lee; Seunghwan Hwang; Michael Jaemin Kim; Jaewan Choi; Jung Ho Ahn (IEEE Trans. Computers, 2022)

MVP: An Efficient CNN Accelerator with Matrix, Vector, and Processing-Near-Memory Units. - Sunjung Lee; Jaewan Choi; Wonkyung Jung; Byeongho Kim; Jaehyun Park 006; Hweesoo Kim; Jung Ho Ahn (ACM Trans. Design Autom. Electr. Syst., 2022)

SHADOW: Preventing Row Hammer in DRAM with Intra-Subarray Row Shuffling. - Minbok Wi; Jaehyun Park 006; Seoyoung Ko; Michael Jaemin Kim; Nam Sung Kim; Eojin Lee; Jung Ho Ahn (HPCA, 2023)

SHARP: A Short-Word Hierarchical Accelerator for Robust and Practical Fully Homomorphic Encryption. - Jongmin Kim 007; Sangpyo Kim; Jaewan Choi; Jaiyoung Park; Donghwan Kim; Jung Ho Ahn (ISCA, 2023)

How to Kill the Second Bird with One ECC: The Pursuit of Row Hammer Resilient DRAM. - Michael Jaemin Kim; Minbok Wi; Jaehyun Park 006; Seoyoung Ko; Jaeyoung Choi; Hwayong Nam; Nam Sung Kim; Jung Ho Ahn; Eojin Lee (MICRO, 2023)

Demystifying CXL Memory with Genuine CXL-Ready Systems and Devices. - Yan Sun; Yifan Yuan; Zeduo Yu; Reese Kuper; Chihun Song; Jinghan Huang 001; Houxiang Ji; Siddharth Agarwal; Jiaqi Lou; Ipoom Jeong; Ren Wang 001; Jung Ho Ahn; et al. (MICRO, 2023)

Unleashing the Potential of PIM: Accelerating Large Batched Inference of Transformer-Based Generative Models. - Jaewan Choi; Jaehyun Park 006; Kwanhee Kyung; Nam Sung Kim; Jung Ho Ahn (IEEE Comput. Archit. Lett., 2023)

A Hardware-Friendly Tiled Singular-Value Decomposition-Based Matrix Multiplication for Transformer-Based Models. - Hailong Li; Jaewan Choi; Yongsuk Kwon; Jung Ho Ahn (IEEE Comput. Archit. Lett., 2023)

ADT: Aggressive Demotion and Promotion for Tiered Memory. - Yaebin Moon; Wanju Doh; Kwanhee Kyung; Eojin Lee; Jung Ho Ahn (IEEE Comput. Archit. Lett., 2023)

X-ray: Discovering DRAM Internal Structure and Error Characteristics by Issuing Memory Commands. - Hwayong Nam; Seungmin Baek; Minbok Wi; Michael Jaemin Kim; Jaehyun Park 006; Chihun Song; Nam Sung Kim; Jung Ho Ahn (IEEE Comput. Archit. Lett., 2023)

HyPHEN: A Hybrid Packing Method and Optimizations for Homomorphic Encryption-Based Neural Networks. - Donghwan Kim; Jaiyoung Park; Jongmin Kim 007; Sangpyo Kim; Jung Ho Ahn (CoRR, 2023)

RETROSPECTIVE: Corona: System Implications of Emerging Nanophotonic Technology. - Dana Vantrease; Robert Schreiber; Matteo Monchiero; Moray McLaren; Norman P. Jouppi; Marco Fiorentino; Al Davis; Nathan L. Binkert; Raymond G. Beausoleil; Jung Ho Ahn (CoRR, 2023)

Toward Practical Privacy-Preserving Convolutional Neural Networks Exploiting Fully Homomorphic Encryption. - Jaiyoung Park; Donghwan Kim; Jongmin Kim 007; Sangpyo Kim; Wonkyung Jung; Jung Hee Cheon; Jung Ho Ahn (CoRR, 2023)

NeuJeans: Private Neural Network Inference with Joint Optimization of Convolution and Bootstrapping. - Jae Hyung Ju; Jaiyoung Park; Jongmin Kim 007; Donghwan Kim; Jung Ho Ahn (CoRR, 2023)

High-precision RNS-CKKS on fixed but smaller word-size architectures: theory and application. - Rashmi Agrawal 001; Jung Ho Ahn; Flávio Bergamaschi; Ro Cammarota; Jung Hee Cheon; Fillipe D. M. de Souza; Huijing Gong; Minsik Kang; Duhyeong Kim; Jongmin Kim 007; Hubert de Lassus; Jai Hyun Park; et al. (IACR Cryptol. ePrint Arch., 2023)

MaPHeA: A Framework for Lightweight Memory Hierarchy-aware Profile-guided Heap Allocation. - Deok-Jae Oh; Yaebin Moon; Do Kyu Ham; Tae Jun Ham; Yongjun Park 001; Jae W. Lee; Jung Ho Ahn; Eojin Lee (ACM Trans. Embed. Comput. Syst., 2023)

AttAcc! Unleashing the Power of PIM for Batched Transformer-based Generative Model Inference. - Jaehyun Park 006; Jaewan Choi; Kwanhee Kyung; Michael Jaemin Kim; Yongsuk Kwon; Nam Sung Kim; Jung Ho Ahn (ASPLOS (2), 2024)

TAROT: A CXL SmartNIC-Based Defense Against Multi-bit Errors by Row-Hammer Attacks. - Chihun Song; Michael Jaemin Kim; Tianchen Wang; Houxiang Ji; Jinghan Huang 001; Ipoom Jeong; Jaehyun Park 006; Hwayong Nam; Minbok Wi; Jung Ho Ahn; Nam Sung Kim (ASPLOS (3), 2024)

NeuJeans: Private Neural Network Inference with Joint Optimization of Convolution and FHE Bootstrapping. - Jae Hyung Ju; Jaiyoung Park; Jongmin Kim 007; Minsik Kang; Donghwan Kim; Jung Hee Cheon; Jung Ho Ahn (CCS, 2024)

An LPDDR-based CXL-PNM Platform for TCO-efficient Inference of Transformer-based Large Language Models. - Sangsoo Park; KyungSoo Kim 003; Jinin So; Jin Jung; Jonggeon Lee; Kyoungwan Woo; Nayeon Kim 006; Younghyun Lee; Hyungyo Kim; Yongsuk Kwon; Jinhyun Kim; Jieun Lee; et al. (HPCA, 2024)

IDT: Intelligent Data Placement for Multi-tiered Main Memory with Reinforcement Learning. - Juneseo Chang; Wanju Doh; Yaebin Moon; Eojin Lee; Jung Ho Ahn (HPDC, 2024)

CLAY: CXL-based Scalable NDP Architecture Accelerating Embedding Layers. - Sungmin Yun 001; Hwayong Nam; Kwanhee Kyung; Jaehyun Park 006; Byeongho Kim; Yongsuk Kwon; Eojin Lee; Jung Ho Ahn (ICS, 2024)

DRAMScope: Uncovering DRAM Microarchitecture and Characteristics by Issuing Memory Commands. - Hwayong Nam; Seungmin Baek; Minbok Wi; Michael Jaemin Kim; Jaehyun Park 006; Chihun Song; Nam Sung Kim; Jung Ho Ahn (ISCA, 2024)

Native DRAM Cache: Re-architecting DRAM as a Large-Scale Cache for Data Centers. - Yesin Ryu; Yoojin Kim; Giyong Jung; Jung Ho Ahn; Jungrae Kim (ISCA, 2024)

Duplex: A Device for Large Language Models with Mixture of Experts, Grouped Query Attention, and Continuous Batching. - Sungmin Yun 001; Kwanhee Kyung; Juhwan Cho; Jaewan Choi; Jongmin Kim 007; Byeongho Kim; Sukhan Lee 002; Kyomin Sohn; Jung Ho Ahn (MICRO, 2024)

CiFHER: A Chiplet-Based FHE Accelerator with a Resizable Structure. - Sangpyo Kim; Jongmin Kim 007; Jaeyoung Choi; Jung Ho Ahn (SEED, 2024)

HyPHEN: A Hybrid Packing Method and Its Optimizations for Homomorphic Encryption-Based Neural Networks. - Donghwan Kim; Jaiyoung Park; Jongmin Kim 007; Sangpyo Kim; Jung Ho Ahn (IEEE Access, 2024)

Accelerating Programmable Bootstrapping Targeting Contemporary GPU Microarchitecture. - Hyesung Ji; Sangpyo Kim; Jaewan Choi; Jung Ho Ahn (IEEE Comput. Archit. Lett., 2024)

Cheddar: A Swift Fully Homomorphic Encryption Library for CUDA GPUs. - Jongmin Kim 007; Wonseok Choi 015; Jung Ho Ahn (CoRR, 2024)

DRAMScope: Uncovering DRAM Microarchitecture and Characteristics by Issuing Memory Commands. - Hwayong Nam; Seungmin Baek; Minbok Wi; Michael Jaemin Kim; Jaehyun Park 006; Chihun Song; Nam Sung Kim; Jung Ho Ahn (Zenodo, 2024)

DRAMScope: Uncovering DRAM Microarchitecture and Characteristics by Issuing Memory Commands. - Hwayong Nam; Seungmin Baek; Minbok Wi; Michael Jaemin Kim; Jaehyun Park 006; Chihun Song; Nam Sung Kim; Jung Ho Ahn (Zenodo, 2024)

DRAMScope: Uncovering DRAM Microarchitecture and Characteristics by Issuing Memory Commands. - Hwayong Nam; Seungmin Baek; Minbok Wi; Michael Jaemin Kim; Jaehyun Park 006; Chihun Song; Nam Sung Kim; Jung Ho Ahn (Zenodo, 2024)

GraNDe: Efficient Near-Data Processing Architecture for Graph Neural Networks. - Sungmin Yun 001; Hwayong Nam; Jaehyun Park 006; Byeongho Kim; Jung Ho Ahn; Eojin Lee (IEEE Trans. Computers, 2024)

Marionette: A RowHammer Attack via Row Coupling. - Seungmin Baek; Minbok Wi; Seonyong Park; Hwayong Nam; Michael Jaemin Kim; Nam Sung Kim; Jung Ho Ahn (ASPLOS (1), 2025)

M5: Mastering Page Migration and Memory Management for CXL-based Tiered Memory Systems. - Yan Sun; Jongyul Kim 001; Zeduo Yu; Jiyuan Zhang 003; Siyuan Chai; Michael Jaemin Kim; Hwayong Nam; Jaehyun Park 006; Eojin Na; Yifan Yuan; Ren Wang 001; Jung Ho Ahn; et al. (ASPLOS (2), 2025)

PET: Proactive Demotion for Efficient Tiered Memory Management. - Wanju Doh; Yaebin Moon; Seoyoung Ko; Seunghwan Chung; Kwanhee Kyung; Eojin Lee; Jung Ho Ahn (EuroSys, 2025)

Anaheim: Architecture and Algorithms for Processing Fully Homomorphic Encryption in Memory. - Jongmin Kim 007; Sungmin Yun 001; Hyesung Ji; Wonseok Choi 015; Sangpyo Kim; Jung Ho Ahn (HPCA, 2025)

Per-Row Activation Counting on Real Hardware: Demystifying Performance Overheads. - Jumin Kim; Seungmin Baek; Minbok Wi; Hwayong Nam; Michael Jaemin Kim; Sukhan Lee 002; Kyomin Sohn; Jung Ho Ahn (IEEE Comput. Archit. Lett., 2025)

Cosmos: A CXL-Based Full In-Memory System for Approximate Nearest Neighbor Search. - Seoyoung Ko; Hyunjeong Shim; Wanju Doh; Sungmin Yun 001; Jinin So; Yongsuk Kwon; Sang-Soo Park; Si-Dong Roh; Minyong Yoon; Taeksang Song; Jung Ho Ahn (IEEE Comput. Archit. Lett., 2025)

SSD Offloading for LLM Mixture-of-Experts Weights Considered Harmful in Energy Efficiency. - Kwanhee Kyung; Sungmin Yun 001; Jung Ho Ahn (IEEE Comput. Archit. Lett., 2025)

X-PPR: Post Package Repair for CXL Memory. - Chihun Song; Michael Jaemin Kim; Yan Sun; Houxiang Ji; Kyungsan Kim; TaeKyeong Ko; Jung Ho Ahn; Nam Sung Kim (IEEE Comput. Archit. Lett., 2025)

Sudoku: Decomposing DRAM Address Mapping into Component Functions. - Minbok Wi; Seungmin Baek; Seonyong Park; Mattan Erez; Jung Ho Ahn (CoRR, 2025)

Hechi: A Hybrid Approach for Efficient Memory Reclamation Techniques in Mobile Systems. - Wanju Doh; Seoyoung Ko; Michael Jaemin Kim; Jung Ho Ahn (IEEE Embed. Syst. Lett., 2025)

The New LLM Bottleneck: A Systems Perspective on Latent Attention and Mixture-of-Experts. - Sungmin Yun 001; Seonyong Park; Hwayong Nam; Younjoo Lee; Gunjun Lee; Kwanhee Kyung; Sangpyo Kim; Nam Sung Kim; Jongmin Kim 007; Hyungyo Kim; Juhwan Cho; Seungmin Baek; et al. (CoRR, 2025)