A noise optimization technique for integrated low-noise amplifiers. - Jung-Suk Goo; Hee-Tae Ahn; Donald J. Ladwig; Zhiping Yu; Thomas H. Lee; Robert W. Dutton (IEEE J. Solid State Circuits, 2002)

Impact of stress on various circuit characteristics in 65nm PDSOI technology. - Sushant Suryagandh; Mayank Gupta; Zhiyuan Wu; Srinath Krishnan; Mario Pelella; Jung-Suk Goo; Ciby Thuruthiyil; Judy X. An; Brian Q. Chen; Niraj Subba; Luis Zamudio; James Yonemura; et al. (ESSCIRC, 2007)

Compact modeling and simulation of PD-SOI MOSFETs: Current status and challenges. - Jung-Suk Goo; Richard Q. Williams; Glenn O. Workman; Qiang Chen; Sungjae Lee; Edward J. Nowak (CICC, 2008)

Modeling local variation of low-frequency noise in MOSFETs via sum of lognormal random variables. - Bo Yu; Xin Li; James Yonemura; Zhiyuan Wu; Jung-Suk Goo; Ciby Thuruthiyil; Ali Icel (CICC, 2012)

Reliability-Conscious MOSFET Compact Modeling with Focus on the Defect-Screening Effect of Hot-Carrier Injection. - Pratik B. Vyas; Ninad Pimparkar; Robert Tu; Wafa Arfaoui; Germain Bossu; Mahesh Siddabathula; Steffen Lehmann; Jung-Suk Goo; Ali B. Icel (IRPS, 2021)