An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme. - Kyu-Hyoun Kim; Uksong Kang; Hoeju Chung; Dukha Park; Woo-Seop Kim; Young-Chan Jang; Moon-Sook Park; Hoon Lee; Jinyoung Kim; Jung Sunwoo; Hwan-Wook Park; Hyun-Kyung Kim; et al. (ISSCC, 2006)

BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel. - Young-Chan Jang; Hoeju Chung; Youngdon Choi; Hwan-Wook Park; Jaekwan Kim 003; Soouk Lim; Jung Sunwoo; Moon-Sook Park; Hyung-Seuk Kim; Sang-Yun Kim; Yun-Sang Lee; Woo-Seop Kim; et al. (IEEE J. Solid State Circuits, 2009)

A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW. - Hoeju Chung; Byung-Hoon Jeong; ByungJun Min; Youngdon Choi; Beak-Hyung Cho; Junho Shin; Jinyoung Kim; Jung Sunwoo; Joon-min Park; Qi Wang; Yong-jun Lee; Sooho Cha; et al. (ISSCC, 2011)

A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth. - Youngdon Choi; Ickhyun Song; Mu-Hui Park; Hoeju Chung; Sanghoan Chang; Beakhyoung Cho; Jinyoung Kim; Younghoon Oh; Dukmin Kwon; Jung Sunwoo; Junho Shin; Yoohwan Rho; et al. (ISSCC, 2012)