A 112-Gb/s PAM-4 Transmitter with 8: 1 MUX in 28-nm CMOS. - Jung-Woo Sull; Hyungrok Do; Deog-Kyoon Jeong (ISOCC, 2020)

A 64 Gb/s 2.09 pJ/b PAM-4 VCSEL Transmitter with Bandwidth Extension Techniques in 40 nm CMOS. - Hyungrok Do; Jung-Woo Sull; Seunghyun Lee; Kwangho Lee; Deog-Kyoon Jeong (A-SSCC, 2021)

0.76-mW/pF/GHz, 7-GHz Quadrature Resonant Clock With Frequency Tuning Capacitor and Amplitude Control Feedback Loop. - Chang-Soo Yoon; Han-Gon Ko; Byung-Jun Kang; Jung-Woo Sull; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 68.7-fJ/b/mm 375-GB/s/mm Single-Ended PAM-4 Interface with Per-Pin Training Sequence for the Next-Generation HBM Controller. - Jung-Hun Park; Kwang-Hoon Lee; Yongjae Lee; Jung-Woo Sull; Yoonho Song; Sanghee Lee 002; Hyeonseok Lee; Hoyeon Cho; Jonghyun Oh; Han-Gon Ko; Deog-Kyoon Jeong (VLSI Technology and Circuits, 2022)

An 8-GHz Octa-Phase Error Corrector With Coprime Phase Comparison Scheme in 40-nm CMOS. - Jung-Woo Sull; Soyeong Shin; Jonghyun Oh; Kwang-Hoon Lee; Jihee Kim; Jung-Hun Park; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

An 8-GHz Octa-Phase Clock Corrector with Phase and Duty-Cycle Correction in 40-nm CMOS. - Jung-Woo Sull; Minkyo Shim; Jung-Hun Park; Sanghee Lee 002; Deog-Kyoon Jeong (MWSCAS, 2023)

A 14-to-32-Gb/s Deadzone-Free Referenceless CDR with Autocovariance-based Frequency Detector in 40-nm CMOS Technology. - Hong-Seok Choi; Jae-Geon Lee; Kwang-Ho Lee; Daehyun Koh; Jung-Woo Sull; Hyungrok Do; Chan-Ho Kye; Deog-Kyoon Jeong; Min-Seong Choo (A-SSCC, 2024)

A 50-Gb/s PAM-4 Receiver With Adaptive Phase-Shifting CDR in 28-nm CMOS. - Minkyo Shim; Seungha Roh; Yunhee Lee; Jung-Woo Sull; Deog-Kyoon Jeong; Kwanseo Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)