Backward Propagated Capacitance Model for Register Transfer Level Power Estimation. - Jung Yun Choi; Young Hwan Kim; Kyoung-Rok Cho (VLSI Design, 2001)

Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. - Youngsoo Shin; Sewan Heo; Hyung-Ock Kim; Jung Yun Choi (ASP-DAC, 2007)

Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. - Youngsoo Shin; Sewan Heo; Hyung-Ock Kim; Jung Yun Choi (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Supply Switching With Ground Collapse for Low-Leakage Register Files in 65-nm CMOS. - Hyung-Ock Kim; Bong Hyun Lee; Jong-Tae Kim; Jung Yun Choi; Kyu-Myung Choi; Youngsoo Shin (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics. - Young Moon Kim; Jun Seomun; Hyung-Ock Kim; Kyung Tae Do; Jung Yun Choi; Kee Sup Kim; Matthias Sauer 002; Bernd Becker 001; Subhasish Mitra (CICC, 2013)

Early-life-failure detection using SAT-based ATPG. - Matthias Sauer 002; Young Moon Kim; Jun Seomun; Hyung-Ock Kim; Kyung Tae Do; Jung Yun Choi; Kee Sup Kim; Subhasish Mitra; Bernd Becker 001 (ITC, 2013)

Clock domain crossing aware sequential clock gating. - Jianfeng Liu; Mi-Suk Hong; Kyung Tae Do; Jung Yun Choi; Jaehong Park; Mohit Kumar; Manish Kumar; Nikhil Tripathi; Abhishek Ranjan (DATE, 2015)

Coarse-grained Structural Placement for a Synthesized Parallel Multiplier. - Sungmin Bae; Hyung-Ock Kim; Jung Yun Choi; Jaehong Park (ISPD, 2015)

Adaptive delay monitoring for wide voltage-range operation. - Jongho Kim; Gunhee Lee; Kiyoung Choi; Yonghwan Kim; Wook Kim; Kyung Tae Do; Jung Yun Choi (DATE, 2016)

Sequential analysis driven reset optimization to improve power, area and routability. - Srihari Yechangunja; Raj Shekhar; Mohit Kumar; Nikhil Tripathi; Abhishek Mittal; Abhishek Ranjan; Jianfeng Liu; Minyoung Mo; Kyung Tae Do; Jung Yun Choi; SungHo Park (DATE, 2016)

Application of Deep Reinforcement Learning to Dynamic Verification of DRAM Designs. - Hyojin Choi; In Huh; Seungju Kim; Jeonghoon Ko; Changwook Jeong; Hyeonsik Son; Kiwon Kwon; Joonwan Chai; Younsik Park; Jaehoon Jeong; Daesin Kim; Jung Yun Choi (DAC, 2021)

Accurate Layout-Dependent Effect Model in 10 nm-Class DRAM Process Using Area-Efficient Array Test Circuits. - Seyoung Kim; Seungho Yang; Hyein Lim; Hyein Lee 008; Jongwook Jeon; Jung Yun Choi; Jaeha Kim (IEEE Access, 2023)

LayNet: Layout Size Prediction for Memory Design Using Graph Neural Networks in Early Design Stage. - Hye Rim Ji; Jong Seong Kim; Jung Yun Choi; Jee Hyong Lee 001 (ASPDAC, 2024)

Estimation of Remaining Useful Life from the Aging Degradation in IC Performance Parameters. - Jiho Lee; Jiwon Kim; Seyoung Kim; Young-Yun Lee; Kanghyun Seo; Jung Yun Choi (IRPS, 2025)