A 6-bit drift-resilient readout scheme for multi-level Phase-Change Memory. - Aravinthan Athmanathan; Milos Stanisavljevic; Junho Cheon; Seokjoon Kang; Changyong Ahn; Junghyuk Yoon; Min-Chul Shin; Taekseung Kim; Nikolaos Papandreou; Haris Pozidis; Evangelos Eleftheriou (A-SSCC, 2014)

Auto-Scaling Overdrive Method Using Adaptive Charge Amplification for PRAM Write Performance Enhancement. - Sukhwan Choi; Hyunsik Kim; Seungchul Jung; Si-Duk Sung; Young-sub Yuk; Hyuck-Sang Yim; Yoonjae Shin; Junho Cheon; Changyong Ahn; Taekseung Kim; Yongki Brave Kim; Gyu-Hyeong Cho (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Non-resistance metric based read scheme for multi-level PCRAM in 25 nm technology. - Junho Cheon; Insoo Lee; Changyong Ahn; Milos Stanisavljevic; Aravinthan Athmanathan; Nikolaos Papandreou; Haris Pozidis; Evangelos Eleftheriou; Min-Chul Shin; Taekseung Kim; Jong-Ho Kang; Jun Hyun Chun (CICC, 2015)

A 15 µm-Pitch, 8.7-ENOB, 13-Mcells/sec Logarithmic Readout Circuit for Multi-Level Cell Phase Change Memory. - Dong-Hwan Jin; Ji-Wook Kwon; Hyeon-June Kim; Sun-Il Hwang; Min-Chul Shin; Junho Cheon; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2015)

Improvement of MAC Accuracy using Oxygen Diffusion Barriers in Resistive Synaptic Cell Arrays. - Youngjae Kwon; Won-Tae Koo; Sangsu Park; Dong Ik Suh; Gunhee Lee; Hyung Dong Lee; Youngbae Ahn; Dohee Kim; Seungwook Ryu; Hoseok Em; Seokjoon Kang; Chang Won Jeong; et al. (IMW, 2024)

First Demonstration of Fully Integrated 16 nm Half-Pitch Selector Only Memory (SOM) for Emerging CXL Memory. - Myoungsub Kim; Yooncheol Bae; Jaehyuk Park; Jeongho Yeon; Hyungjoon Shim; Sehyun Jin; Hyunsoo Kim; Sangchul Oh; Gapsok Do; Dongyeol Yun; Hyung Dong Lee; David Ahn; et al. (VLSI Technology and Circuits, 2024)