An asynchronous delay line TDC for ADPLL in 0.13um CMOS. - Chunhui Li; Lei Ma; Junhui Xiang; Hao Min (ASICON, 2015)

A low power TDC with 0.5ps resolution for ADPLL in 40nm CMOS. - Xusong Liu; Lei Ma; Junhui Xiang; Na Yan; Haolv Xie; Xiaowei Cai (ASICON, 2015)

A fully logic CMOS compatible non-volatile memory for low power IoT applications. - Yu Wang 046; Junhui Xiang; Xianliang Chen; Tao Yang 022; Na Yan; Hao Min (IOT, 2015)

An Active Tag Using Carrier Recovery Circuit for EPC Gen2 Passive UHF RFID Systems. - Tao Yang 022; Junhui Xiang; Yu Wang 046; Xi Tan 001; Junyu Wang; Na Yan; Lirong Zheng 001; Hao Min (IEEE Trans. Ind. Electron., 2018)

A Low Power All-Digital PLL With -40dBc In-Band Fractional Spur Suppression for NB-IoT Applications. - Na Yan; Lei Ma; Yongxin Xu; Sizheng Chen; Xusong Liu; Junhui Xiang; Hao Min (IEEE Access, 2019)