A 32-bit microprocessor with high performance bit-map manipulation instructions. - Toru Shimizu; Shunichi Iwata; Yuichi Saito; Toyohiko Yoshida; Masahito Matsuo; Junichi Hinata; Kazunori Saito (ICCD, 1989)

A 1.71-million transistor CMOS CPU chip with a testable cache architecture. - Yuichi Saito; Yukihiko Shimazu; Tom Shimizu; Kenji Shirai; Isao Fujioka; Yoshitetsu Nishiwaki; Junichi Hinata; Yoshiki Shimotsuma; Masayoshi Sakao (IEEE J. Solid State Circuits, 1993)