An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm. - Masayuki Miyama; Osamu Tooyama; N. Takamatsu; T. Kodake; K. Nakamura; A. Kato; Junichi Miyakoshi; K. Hashimoto; Shigenobu Komatsu; M. Yagi; Masao Morimoto; Kazuo Taki; et al. (CICC, 2002)

A sub-mW MPEG-4 motion estimation processor core for mobile video application. - Junichi Miyakoshi; Yuri Kuroda; Masayuki Miyama; Kosuke Imamura; Hideo Hashimoto; Masahiko Yoshimoto (CICC, 2003)

A sub-mW MPEG-4 motion estimation processor core for mobile video application. - Yuki Kuroda; Junichi Miyakoshi; Masayuki Miyama; Kousuke Imamura; Hideo Hashimoto; Masahiko Yoshimoto (ASP-DAC, 2004)

A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation. - Junichi Miyakoshi; Yuichiro Murachi; Koji Hamano; Tetsuro Matsuno; Masayuki Miyama; Masahiko Yoshimoto (IEICE Trans. Electron., 2005)

A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application. - Yuichiro Murachi; Koji Hamano; Tetsuro Matsuno; Junichi Miyakoshi; Masayuki Miyama; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering. - Hidehiro Fujiwara; Koji Nii; Junichi Miyakoshi; Yuichiro Murachi; Yasuhiro Morita; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISLPED, 2006)

A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing. - Junichi Miyakoshi; Yuichiro Murachi; Masaki Hamamoto; Takahiro Iinuma; Tomokazu Ishihara; Hiroshi Kawaguchi 001; Masahiko Yoshimoto; Tetsuro Matsuno (VLSI-SoC, 2006)

VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation. - Noriyuki Minegishi; Junichi Miyakoshi; Yuki Kuroda; Tadayoshi Katagiri; Yuki Fukuyama; Ryo Yamamoto; Masayuki Miyama; Kousuke Imamura; Hideo Hashimoto; Masahiko Yoshimoto (IEICE Trans. Electron., 2006)

A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing. - Junichi Miyakoshi; Yuichiro Murachi; Tomokazu Ishihara; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2006)

A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture. - Junichi Miyakoshi; Yuichiro Murachi; Tetsuro Matsuno; Masaki Hamamoto; Takahiro Iinuma; Tomokazu Ishihara; Hiroshi Kawaguchi 001; Masayuki Miyama; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond. - Yasuhiro Morita; Hidehiro Fujiwara; Hiroki Noguchi; Kentaro Kawakami; Junichi Miyakoshi; Shinji Mikami; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

An H.264/AVC MP@L4.1 quarter-pel motion estimation processor VLSI for real-time MBAFF encoding. - Kosuke Mizuno; Junichi Miyakoshi; Yuichiro Murachi; Masaki Hamamoto; Takahiro Iinuma; Tomokazu Ishihara; Fang Yin; Jangchung Lee; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ICECS, 2008)

A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding. - Yuichiro Murachi; Kosuke Mizuno; Junichi Miyakoshi; Masaki Hamamoto; Takahiro Iinuma; Tomokazu Ishihara; Fang Yin; Jangchung Lee; Tetsuya Kamino; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISCAS, 2008)

A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition. - Yuichiro Murachi; Yuki Fukuyama; Ryo Yamamoto; Junichi Miyakoshi; Hiroshi Kawaguchi 001; Hajime Ishihara; Masayuki Miyama; Yoshio Matsuda; Masahiko Yoshimoto (IEICE Trans. Electron., 2008)

A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer. - Yuichiro Murachi; Junichi Miyakoshi; Masaki Hamamoto; Takahiro Iinuma; Tomokazu Ishihara; Fang Yin; Jangchung Lee; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2008)

Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering. - Hidehiro Fujiwara; Koji Nii; Hiroki Noguchi; Junichi Miyakoshi; Yuichiro Murachi; Yasuhiro Morita; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEEE Trans. Very Large Scale Integr. Syst., 2008)

A 45nm 37.3GOPS/W heterogeneous multi-core SoC. - Yoichi Yuyama; Masayuki Ito; Yoshikazu Kiyoshige; Yusuke Nitta; Shigezumi Matsui; Osamu Nishii; Atsushi Hasegawa; Makoto Ishikawa; Tetsuya Yamada; Junichi Miyakoshi; Koichi Terada; Tohru Nojiri; et al. (ISSCC, 2010)

A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core. - Osamu Nishii; Yoichi Yuyama; Masayuki Ito; Yoshikazu Kiyoshige; Yusuke Nitta; Makoto Ishikawa; Tetsuya Yamada; Junichi Miyakoshi; Yasutaka Wada; Keiji Kimura; Hironori Kasahara; Hideo Maejima (IEICE Trans. Electron., 2011)

Size-adaptive hepatocellular carcinoma detection from 3D CT images based on the level set method. - Shuntaro Yui; Junichi Miyakoshi; Kazuki Matsuzaki; Toshiyuki Irie; Ryo Kurazume (Computer-Aided Diagnosis, 2012)

Metastatic liver tumor detection from 3D CT images using a level set algorithm with liver-edge term. - Junichi Miyakoshi; Shuntaro Yui; Kazuki Matsuzaki; Toshiyuki Irie (Image Processing, 2012)

False-positive reduction of liver tumor detection using ensemble learning method. - Atsushi Miyamoto; Junichi Miyakoshi; Kazuki Matsuzaki; Toshiyuki Irie (Image Processing, 2013)

Subjective-objective policy making approach: Coupling of resident-values multiple regression analysis with value-indices, multi-agent-based simulation. - Misa Owa; Junichi Miyakoshi; Takeshi Kato (CoRR, 2023)

Modeling pattern formation in communities by using information particles. - Junichi Miyakoshi (CoRR, 2023)

Mixbiotic society measures: Assessment of community well-going as living system. - Takeshi Kato; Junichi Miyakoshi; Tadayuki Matsumura; Ryuji Mine; Hiroyuki Mizuno; Yasuo Deguchi (CoRR, 2023)

Mixbiotic society measures: Comparison of organizational structures based on communication simulation. - Takeshi Kato; Junichi Miyakoshi; Tadayuki Matsumura; Yasuyuki Kudo; Ryuji Mine; Hiroyuki Mizuno; Yasuo Deguchi (CoRR, 2023)

Social Co-OS: Cyber-human social Co-operating system. - Takeshi Kato; Yasuyuki Kudo; Junichi Miyakoshi; Misa Owa; Yasuhiro Asa; Takashi Numata; Ryuji Mine; Hiroyuki Mizuno (IET Cyper-Phys. Syst.: Theory & Appl., 2023)

Market, power, gift, and concession economies: Comparison using four-mode primitive network models. - Takeshi Kato; Junichi Miyakoshi; Misa Owa; Ryuji Mine (CoRR, 2025)