A 68-ns 4-Mbit CMOS EPROM with high-noise-immunity design. - Kenichi Imamiya; Jun-ichi Miyamoto; Shigeru Atsumi; Nobuaki Ohtsuka; Yukinori Muroya; Toshiyuki Sako; Masao Higashino; Yumiko Iyama; Seiichi Mori; Yoichi Ohshima; Hitoshi Araki; Yukio Kaneko; et al. (IEEE J. Solid State Circuits, 1990)

Multi-Step Stress Test for Yield Improvement of 16Mbit EPROMs with Redundancy Scheme. - Jun-ichi Miyamoto; Nobuaki Ohtsuka; Ken-ichi Imamiya; Naoto Tomita; Yumiko Iyama (ITC, 1991)

A 62-ns 16-Mb CMOS EPROM with voltage stress relaxation technique. - Naoto Tomita; Nobuaki Ohtsuka; Jun-ichi Miyamoto; Ken-ichi Imamiya; Yumiko Iyama; Seiichi Mori; Yoichi Ohshima; Norihisa Arai; Yukio Kaneko; Eiji Sakagami; Kuniyoshi Yoshikawa; Sumio Tanaka (IEEE J. Solid State Circuits, 1991)

Optimum redundancy design for new-generation EPROMs based on yield analysis of previous generation. - Ken-ichi Imamiya; Jun-ichi Miyamoto; Nobuaki Ohtuska; Naoto Tomita; Yumiko Iyama (VTS, 1992)

A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM. - Yoshihisa Iwata; Ken-ichi Imamiya; Yoshihisa Sugiura; Hiroshi Nakamura; Hideko Oodaira; Masaki Momodomi; Yasuo Itoh; Toshiharu Watanabe; Hitoshi Araki; Kazuhito Narita; Kazunori Masuda; Junichi Miyamoto (IEEE J. Solid State Circuits, 1995)

A 120-mm2 64-Mb NAND flash memory achieving 180 ns/Byte effective program speed. - Jin-Ki Kim; Koji Sakui; Sung-Soo Lee; Yasuo Itoh; Suk-Chon Kwon; Kazuhisa Kanazawa; Ki-Jun Lee; Hiroshi Nakamura; Kang-Young Kim; Toshihiko Himeno; Jang-Rae Kim; Kazushige Kanda; et al. (IEEE J. Solid State Circuits, 1997)

A statistical method for analyzing lifetime of a series-connected battery cells. - Daisuke Sasaki; Shuji Tsukiyama; Mariko Matsunaga; Junichi Miyamoto; Shingo Takahashi (ISCIT, 2015)

On-line lithium-ion battery state of health estimation using aging-related impedance identification with optimization. - Sho Ohtani; Junichi Miyamoto; Hiroshi Kajitani; Shingo Takahashi (ISGT Asia, 2015)