Investigation of wireless power transfer in multi-coil environment. - Hyeonseok Hwang; Bumsoo Lee; Junil Moon; Se-Chun Park; Chan-Hui Jeong; Soo-Won Kim (ICCE, 2014)

An analysis of magnetic resonance coupling effects on wireless power transfer by coil inductance and placement. - Hyeonseok Hwang; Junil Moon; Bumsoo Lee; Chan-Hui Jeong; Soo-Won Kim (IEEE Trans. Consumer Electron., 2014)

Design of a 169% locking-range frequency divider with programmable input sensitivity. - Byeonghak Jo; Hyeonseok Hwang; Junil Moon; Seung-Baek Park; Soo-Won Kim (ICCE, 2015)

Analysis of receiver circuit efficiency for wireless power transfer system according to operating frequency variation. - Junil Moon; Hee-am Shin; Hyunwook Jeong; Soo-Won Kim (ISCE, 2015)

An inverter layout technique for propagation delay minimization. - Ji-Hak Yu; Chan-Keun Kwon; Junil Moon; Soo-Won Kim (ISCE, 2015)

Optimization of resonant inductive links for wireless power transfer. - Hyeonseok Hwang; Byeonghak Jo; Junil Moon; Chan-Keun Kwon; Baekseok Ko; Soo-Won Kim (ICCE, 2016)

Design of low-power, fast-transient-response, capacitor-less low-dropout regulator for mobile applications. - Junil Moon; Jinhoon Hyun; Soo-Won Kim (IEICE Electron. Express, 2016)

A 12-Bit 500-MS/s Current Steering CMOS DAC for High-Speed PLC Modems. - Chan-Keun Kwon; Junil Moon; Soo-Won Kim (J. Circuits Syst. Comput., 2016)

Design of a 5-W power receiver for 6.78 MHz resonant wireless power transfer system with power supply switching circuit. - Junil Moon; Hyeonseok Hwang; Byeonghak Jo; Hee-am Shin; Soo-Won Kim (IEEE Trans. Consumer Electron., 2016)

A 1.3 V input fast-transient-response time digital low-dropout regulator with a VSSa generator for DVFS system. - Young-Jae Min; Chan-Hui Jeong; Junil Moon; Youngsun Han; Soo-Won Kim; Chulwoo Kim (IEICE Electron. Express, 2017)

A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization. - Myeong-Jae Park; Ho Sung Cho; Tae-Sik Yun; Sangjin Byeon; Young Jun Koo; Sang-Sic Yoon; Dong-Uk Lee; Seokwoo Choi; Ji Hwan Park; Jinhyung Lee; Kyungjun Cho; Junil Moon; et al. (ISSCC, 2022)

A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization. - Myeong-Jae Park; Jinhyung Lee; Kyungjun Cho; Ji Hwan Park; Junil Moon; Sung-Hak Lee; Tae-Kyun Kim 001; Sanghoon Oh; Seokwoo Choi; Yongsuk Choi; Ho Sung Cho; Tae-Sik Yun; et al. (IEEE J. Solid State Circuits, 2023)

13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization. - Jinhyung Lee; Kyungjun Cho; Chang Kwon Lee; Yeonho Lee 002; Jae-Hyung Park; Su-Hyun Oh; Yucheon Ju; Chunseok Jeong; Ho Sung Cho; Jaeseung Lee; Tae-Sik Yun; Jin Hee Cho; et al. (ISSCC, 2024)