A 40-Mpixel/s bit block transfer graphics processor. - Masahiko Sumi; Shigeru Tanaka; Naoyuki Kai; Yuichi Miyazawa; Masato Nagamatsu; Tsutomu Minagawa; Ichiro Nagashima; Tsuneo Hamai; Junji Mori; Tatsuo Noguchi (IEEE J. Solid State Circuits, 1989)

A 15-ns 32*32-b CMOS multiplier with an improved parallel structure. - Masato Nagamatsu; Shigeru Tanaka; Junji Mori; Katsusi Hirano; Tatsuo Noguchi; Kazuhisa Hatanaka (IEEE J. Solid State Circuits, 1990)

A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology. - Junji Mori; Masato Nagamatsu; Masashi Hirano; Shigeru Tanaka; Makoto Noda; Yoshiaki Toyoshima; Kazuhiro Hashimoto; Hiroyuki Hayashida; Kenji Maeguchi (IEEE J. Solid State Circuits, 1991)

A 320 MFLOPS CMOS floating-point processing unit for superscalar processors. - Nobuhiro Ide; Hiroto Fukuhisa; Yoshihisa Kondo; Takeshi Yoshida; Masato Nagamatsu; Junji Mori; Itaru Yamazaki; Kiyoyi Ueno (IEEE J. Solid State Circuits, 1993)

Testability Features of R10000 Microprocessor. - Junji Mori; Ben Mathew; Dave Burns; Yeuk-Hai Mok (Asian Test Symposium, 1997)