500-Mb/s nonprecharged data bus for high-speed DRAM's. - Miyoshi Saito; Junji Ogawa; Hirotaka Tamura; Shigetoshi Wakayama; Hisakatsu Araki; Tsz-Shing Cheung; Kohtaroh Gotoh; Tadao Aikawa; Takaaki Suzuki; Masao Taguchi; Takeshi Imamura (IEEE J. Solid State Circuits, 1998)

A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro. - Junji Ogawa; Mark Horowitz (Intelligent Memory Systems, 2000)

A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process. - Yoshiyasu Doi; Syunitirou Masaki; Takaya Chiba; Hirohito Higashi; Hisakatsu Yamaguchi; Hideki Takauchi; Hideki Ishida; Kohtaroh Gotoh; Junji Ogawa; Hirotaka Tamura (CICC, 2005)

A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique. - Yusuke Okaniwa; Hirotaka Tamura; Masaya Kibune; Daisuke Yamazaki; Tsz-Shing Cheung; Junji Ogawa; Nestoras Tzartzanis; William W. Walker; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2005)

A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS. - Yasumoto Tomita; Masaya Kibune; Junji Ogawa; William W. Walker; Hirotaka Tamura; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2005)

A 20Gb/s Bidirectional Transceiver Using a Resistor-Transconductor Hybrid. - Yasumoto Tomita; Hirotaka Tamura; Masaya Kibune; Junji Ogawa; Kohtaroh Gotoh; Tadahiro Kuroda (ISSCC, 2006)

Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies. - Hirotaka Tamura; Masaya Kibune; Hisakatsu Yamaguchi; Kouichi Kanda; Kohtaroh Gotoh; Hideki Ishida; Junji Ogawa (IEICE Trans. Electron., 2006)

A 40-to-44Gb/s 3? Oversampling CMOS CDR/1: 16 DEMUX. - Nikola Nedovic; Nestoras Tzartzanis; Hirotaka Tamura; Francis M. Rotella; Magnus Wiklund; Yuma Mizutani; Yusuke Okaniwa; Tadahiro Kuroda; Junji Ogawa; William W. Walker (ISSCC, 2007)

18-GHz Clock Distribution Using a Coupled VCO Array. - Takayuki Shibasaki; Hirotaka Tamura; Kouichi Kanda; Hisakatsu Yamaguchi; Junji Ogawa; Tadahiro Kuroda (IEICE Trans. Electron., 2007)

A 40-44 Gb/s 3 × Oversampling CMOS CDR/1: 16 DEMUX. - Nikola Nedovic; Nestoras Tzartzanis; Hirotaka Tamura; Francis M. Rotella; Magnus Wiklund; Yuma Mizutani; Yusuke Okaniwa; Tadahiro Kuroda; Junji Ogawa; William W. Walker (IEEE J. Solid State Circuits, 2007)

A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-µm CMOS. - Yasumoto Tomita; Hirotaka Tamura; Masaya Kibune; Junji Ogawa; Kohtaroh Gotoh; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2007)

20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range. - Takayuki Shibasaki; Hirotaka Tamura; Kouichi Kanda; Hisakatsu Yamaguchi; Junji Ogawa; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2008)

A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS. - Kouichi Kanda; Hirotaka Tamura; Takuji Yamamoto; Satoshi Matsubara; Masaya Kibune; Yoshiyasu Doi; Takayuki Shibasaki; Nestoras Tzartzanis; Anders Kristensson; Samir Parikh; Satoshi Ide; Yukito Tsunoda; et al. (ISSCC, 2009)

A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS. - Kouichi Kanda; Hirotaka Tamura; Takuji Yamamoto; Satoshi Matsubara; Masaya Kibune; Yoshiyasu Doi; Takayuki Shibasaki; Nestoras Tzartzanis; Anders Kristensson; Samir Parikh; Satoshi Ide; Yukito Tsunoda; et al. (IEEE J. Solid State Circuits, 2009)

A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS. - Hisakatsu Yamaguchi; Hirotaka Tamura; Yoshiyasu Doi; Yasumoto Tomita; Takayuki Hamada; Masaya Kibune; Shuhei Ohmoto; Keita Tateishi; Oleksiy Tyshchenko; Ali Sheikholeslami; Tomokazu Higuchi; Junji Ogawa; et al. (ISSCC, 2010)

Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC. - Yanfei Chen; Xiaolei Zhu 002; Hirotaka Tamura; Masaya Kibune; Yasumoto Tomita; Takayuki Hamada; Masato Yoshioka; Kiyoshi Ishikawa; Takeshi Takayama; Junji Ogawa; Sanroku Tsukamoto; Tadahiro Kuroda (IEICE Trans. Electron., 2010)

A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS. - Nikola Nedovic; Anders Kristensson; Samir Parikh; Subodh M. Reddy; Scott McLeod; Nestoras Tzartzanis; Kouichi Kanda; Takuji Yamamoto; Satoshi Matsubara; Masaya Kibune; Yoshiyasu Doi; Satoshi Ide; et al. (IEEE J. Solid State Circuits, 2010)

A 5-Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS. - Oleksiy Tyshchenko; Ali Sheikholeslami; Hirotaka Tamura; Masaya Kibune; Hisakatsu Yamaguchi; Junji Ogawa (IEEE J. Solid State Circuits, 2010)