A 65nm Logic-Compatible Embedded and Flash Memory for In-Memory Computation of Artificial Neural Networks. - Junjie Mu; Bongjin Kim (ISCAS, 2020)

A 252 Spins Scalable CMOS Ising Chip Featuring Sparse and Reconfigurable Spin Interconnects for Combinatorial Optimization Problems. - Yuqi Su; Junjie Mu; Hyunjoon Kim; Bongjin Kim (CICC, 2021)

A 21×21 Dynamic-Precision Bit-Serial Computing Graph Accelerator for Solving Partial Differential Equations Using Finite Difference Method. - Junjie Mu; Bongjin Kim (ISSCC, 2021)

A 20x28 Spins Hybrid In-Memory Annealing Computer Featuring Voltage-Mode Analog Spin Operator for Solving Combinatorial Optimization Problems. - Junjie Mu; Yuqi Su; Bongjin Kim (VLSI Circuits, 2021)

A Scalable Bit-Serial Computing Hardware Accelerator for Solving 2D/3D Partial Differential Equations Using Finite Difference Method. - Junjie Mu; Chengshuo Yu; Tony Tae-Hyoung Kim; Bongjin Kim (ESSCIRC, 2022)

A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory. - Yuzong Chen 001; Junjie Mu; Hyunjoon Kim; Lu Lu 013; Tony Tae-Hyoung Kim (ISCAS, 2022)

A Scalable CMOS Ising Computer Featuring Sparse and Reconfigurable Spin Interconnects for Solving Combinatorial Optimization Problems. - Yuqi Su; Junjie Mu; Hyunjoon Kim; Bongjin Kim (IEEE J. Solid State Circuits, 2022)

SRAM-Based In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC for Processing Neural Networks. - Junjie Mu; Hyunjoon Kim; Bongjin Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Continuous-Time Ising Machine using Coupled Inverter Chains Featuring Fully-Parallel One-Shot Spin Updates. - Chengshuo Yu; Junjie Mu; Kevin Tshun-Chuan Chai; Tony T. Kim; Bongjin Kim (CICC, 2023)

A Graph-Based Accelerator of Retinex Model with Bit-Serial Computing for Image Processing. - Zhengzhe Wei; Junjie Mu; Zhongzhiguang Lu; Yuanjin Zheng; Tony Tae-Hyoung Kim; Bongjin Kim (ISCAS, 2023)

282-to-607 TOPS/W, 7T-SRAM Based CiM with Reconfigurable Column SAR ADC for Neural Network Processing. - Qibang Zang; Wang Ling Goh; Lu Lu 013; Chengshuo Yu; Junjie Mu; Tony Tae-Hyoung Kim; Bongjin Kim; Dongrui Li; Anh Tuan Do (ISCAS, 2023)

A Bit-Serial Computing Accelerator for Solving Coupled Partial Differential Equations. - Junjie Mu; Chengshuo Yu; Tony Tae-Hyoung Kim; Bongjin Kim (VLSI Technology and Circuits, 2023)

A Time-Domain Wavefront Computing Accelerator With a 32 × 32 Reconfigurable PE Array. - Chengshuo Yu; Junjie Mu; Yuqi Su; Kevin Tshun Chuan Chai; Tony Tae-Hyoung Kim; Bongjin Kim (IEEE J. Solid State Circuits, 2023)

A Dynamic-Precision Bit-Serial Computing Hardware Accelerator for Solving Partial Differential Equations Using Finite Difference Method. - Junjie Mu; Bongjin Kim (IEEE J. Solid State Circuits, 2023)

A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks. - Hyunjoon Kim; Junjie Mu; Chengshuo Yu; Tony Tae-Hyoung Kim; Bongjin Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

BP-SCIM: A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory. - Yuzong Chen 001; Junjie Mu; Hyunjoon Kim; Lu Lu 013; Tony Tae-Hyoung Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Leukocyte subtype classification with multi-model fusion. - Yingying Ding; Xuehui Tang; Yuan Zhuang; Junjie Mu; Shuchao Chen; Shanshan Liu; Sihao Feng; Hongbo Chen (Medical Biol. Eng. Comput., 2023)

A 1-Mb RRAM Macro With 9.8 ns Read Access Time Utilizing Dynamic Reference Voltage for Reliable Sensing Operation. - Junjie Mu; Lu Lu 013; Ju Eon Kim; Byung-Kwon An; Vishal Sharma 004; Arya Jagath Lekshmi; Putu Andhita Dananjaya; Weng Hong Lai; Wen Siang Lew; Tony Tae-Hyoung Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Scalable and Reconfigurable Bit-Serial Compute-Near-Memory Hardware Accelerator for Solving 2-D/3-D Partial Differential Equations. - Junjie Mu; Chengshuo Yu; Tony Tae-Hyoung Kim; Bongjin Kim (IEEE J. Solid State Circuits, 2024)

A Dual 7T SRAM-Based Zero-Skipping Compute- In-Memory Macro With 1-6b Binary Searching ADCs for Processing Quantized Neural Networks. - Chengshuo Yu; Haoge Jiang; Junjie Mu; Kevin Tshun Chuan Chai; Tony Tae-Hyoung Kim; Bongjin Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 1Mb RRAM Macro with Bipolar Forming for Improved Programming Yield and Cell-by-cell Write Verification Scheme. - Byungkwon An; Junjie Mu; Putu Andhita Dananjaya; Weng Hong Lai; Wen Siang Lew; Tony Tae-Hyoung Kim (ISCAS, 2025)

A Graph-Based Accelerator of Retinex Model With Bit-Serial Computing for Image Enhancements. - Zhengzhe Wei; Junjie Mu; Yuanjin Zheng; Tony Tae-Hyoung Kim; Bongjin Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

Design and Optimization of Cooperative MAC Protocol for Mobile Ad Hoc Network-Enabled Train-to-Train Communications. - Junjie Mu; Ruizhe Yang; Meng Li 007; Pengbo Si; Yang Sun 005; Yanhua Sun (IEEE Trans. Veh. Technol., 2025)

Pushing the Limits of Safety: A Technical Report on the ATLAS Challenge 2025. - Zonghao Ying; Siyang Wu; Run Hao; Peng Ying; Shixuan Sun; Pengyu Chen; Junze Chen; Hao Du; Kaiwen Shen; Shangkun Wu; Jiwei Wei; Shiyuan He; et al. (CoRR, 2025)

AGENTSAFE: Benchmarking the Safety of Embodied Agents on Hazardous Instructions. - Aishan Liu; Zonghao Ying; Le Wang; Junjie Mu; Jinyang Guo; Jiakai Wang; Yuqing Ma; Siyuan Liang; Mingchuan Zhang; Xianglong Liu 001; Dacheng Tao (CoRR, 2025)