A 4-Mbit DRAM with 16-bit concurrent ECC. - Toshio Yamada; Hisakazu Kotani; Junko Matsushima; Michihiro Inoue (IEEE J. Solid State Circuits, 1988)

A 50-MHz 8-Mbit video RAM with a column direction drive sense amplifier. - Hisakazu Kotani; Hironori Akamatsu; Junko Matsushima; Shozo Okada; Tsuyoshi Shiragasawa; Takayoshi Yamada; Michihiro Inoue (IEEE J. Solid State Circuits, 1990)