Physics-based Modeling and Simulation of Dual Material Gate(DMG) LDMOS. - Yuehua Dai; Yuan Hu; Qi Liu 010; Daoming Ke; Junning Chen (APCCAS, 2006)

A Compact Equivalent Circuit Model of HVLDMOS and Application in HIVC Design. - Shan Gao; Junning Chen; Daoming Ke; Xiulong Wu (APCCAS, 2006)

The Design of High Performance, Low Power Triple-Track Magnetic Sensor Chip. - Xiulong Wu; Minghua Li; Zhiting Lin; Mengyuan Xi; Junning Chen (Sensors, 2013)

A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier. - Chunyu Peng; Youwu Tao; Wenjuan Lu; Zhengping Li; Xinchun Ji; Jinlong Yan; Junning Chen (IEICE Electron. Express, 2015)

Erratum: A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier [IEICE Electronics Express Vol 12 (2015) No 5 pp 20150102]. - Chunyu Peng; Youwu Tao; Wenjuan Lu; Zhengping Li; Xinchun Ji; Jinlong Yan; Junning Chen (IEICE Electron. Express, 2015)

Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier. - Shoubiao Tan; Wenjuan Lu; Chunyu Peng; Zhengping Li; Youwu Tao; Junning Chen (Frontiers Inf. Technol. Electron. Eng., 2015)

Variation-resilient pipelined timing tracking circuit for SRAM sense amplifier. - Zhengping Li; Chunyu Peng; Wenjuan Lu; Lijun Guan; Youwu Tao; Xincun Ji; Junning Chen (IEICE Electron. Express, 2016)

A Pipeline Replica Bitline Technique for Suppressing Timing Variation of SRAM Sense Amplifiers in a 28-nm CMOS Process. - Zhiting Lin; Xiulong Wu; Zhi Li; Lijun Guan; Chunyu Peng; Changyong Liu; Junning Chen (IEEE J. Solid State Circuits, 2017)

Computational insight into dengue virus NS2B-NS3 protease inhibition: A combined ligand- and structure-based approach. - Junning Chen; Hailun Jiang; Fangfei Li; Baichun Hu; Ying Wang 100; Mingxing Wang; Jian Wang 019; Mao-Sheng Cheng (Comput. Biol. Chem., 2018)

A dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination. - Changyong Liu; Chunyu Peng; Zhiting Lin; Xiulong Wu; Ziyang Chen; Qiang Zhao 007; Xuan Li; Junning Chen; Xuan Zeng 001; Xiangdong Hu (IEICE Electron. Express, 2018)

Offset voltage suppressed sense amplifier with self-adaptive distribution transformation technique. - Chunyu Peng; Lingyu Kong; Xiulong Wu; Zhiting Lin; Hua Xu; Junning Chen; Xuan Zeng 001 (IEICE Electron. Express, 2018)

Average 7T1R Nonvolatile SRAM With R/W Margin Enhanced for Low-Power Application. - Chunyu Peng; Songsong Xiao; Wenjuan Lu; Jingbo Zhang; Xiulong Wu; Junning Chen; Zhiting Lin (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A single event upset tolerant latch with parallel nodes. - Changyong Liu; Nianlong Liu; Zhiting Lin; Xiulong Wu; Chunyu Peng; Qiang Zhao 007; Xuan Li; Junning Chen; Xuan Zeng 001; Xiangdong Hu (IEICE Electron. Express, 2019)

An inverter chain with parallel output nodes for eliminating single-event transient pulse. - Changyong Liu; Zhiting Lin; Xiulong Wu; Chunyu Peng; Qiang Zhao 007; Xuan Li; Junning Chen; Xuan Zeng 001; Xiangdong Hu (IEICE Electron. Express, 2019)

Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application. - Chunyu Peng; Jiati Huang; Changyong Liu; Qiang Zhao 007; Songsong Xiao; Xiulong Wu; Zhiting Lin; Junning Chen; Xuan Zeng 001 (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Challenges and Solutions of the TFET Circuit Design. - Zhiting Lin; Panpan Chen; Le Ye; Xu Yan; Lanzhi Dong; Shuguang Zhang; Zhou Yang 009; Chunyu Peng; Xiulong Wu; Junning Chen (IEEE Trans. Circuits Syst., 2020)

Multiple Sharing 7T1R Nonvolatile SRAM With an Improved Read/Write Margin and Reliable Restore Yield. - Zhiting Lin; Yong Wang 038; Chunyu Peng; Xiulong Wu; Xuan Li; Junning Chen (IEEE Trans. Very Large Scale Integr. Syst., 2020)

In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands. - Zhiting Lin; Honglan Zhan; Xuan Li; Chunyu Peng; Wenjuan Lu; Xiulong Wu; Junning Chen (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Novel Write-Enhanced and Highly Reliable RHPD-12T SRAM Cells for Space Applications. - Qiang Zhao 007; Chunyu Peng; Junning Chen; Zhiting Lin; Xiulong Wu (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Cascade Current Mirror to Improve Linearity and Consistency in SRAM In-Memory Computing. - Zhiting Lin; Honglan Zhan; Zhongwei Chen; Chunyu Peng; Xiulong Wu; Wenjuan Lu; Qiang Zhao 007; Xuan Li; Junning Chen (IEEE J. Solid State Circuits, 2021)

Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports. - Zhiting Lin; Zhiyong Zhu; Honglan Zhan; Chunyu Peng; Xiulong Wu; Yuan Yao; Jianchao Niu; Junning Chen (IEEE J. Solid State Circuits, 2021)

Information sharing model of upstream supply chain based on embedded technology. - Junning Chen (Int. J. Inf. Commun. Technol., 2022)

Offset-Compensation High-Performance Sense Amplifier for Low-Voltage DRAM Based on Current Mirror and Switching Point. - Pei Huang 018; Kuan-Chang Chang; Junlin Ge; Chunyu Peng; Xiulong Wu; Junning Chen; Zhiting Lin (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

In-Memory Multibit Multiplication Based on Bitline Shifting. - Jin Zhang 036; Zhiting Lin; Xiulong Wu; Zhongzhen Tong; Chunyu Peng; Wenjuan Lu; Qiang Zhao 007; Hongbiao Wu; Junning Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Configurable Memory With a Multilevel Shared Structure Enabling In-Memory Computing. - Yue Zhao; Zhiting Lin; Xiulong Wu; Qiang Zhao 007; Wenjuan Lu; Chunyu Peng; Zhongzhen Tong; Junning Chen (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Write-enhanced and radiation-hardened SRAM for multi-node upset tolerance in space-radiation environments. - Qiang Zhao 007; Hanwen Dong; Chunyu Peng; Wenjuan Lu; Zhiting Lin; Junning Chen; Xiulong Wu (Int. J. Circuit Theory Appl., 2023)

In Situ Storing 8T SRAM-CIM Macro for Full-Array Boolean Logic and Copy Operations. - Zhiting Lin; Zhongzhen Tong; Fangming Wang; Jin Zhang 036; Yue Zhao; Peng Sun; Tian Xu; Cheng Zhang; Xingwei Li; Xiulong Wu; Wenjuan Lu; Chunyu Peng; et al. (IEEE J. Solid State Circuits, 2023)

A high charge-discharge stability SRAM 10T1C XOR CIM macro applied in BCAM and Hamming distance. - Li Liu 004; Wei Hu; Zhen Yang; Yiming Wei; Chunyu Peng; Xiulong Wu; Zhiting Lin; Wenjuan Lu; Yongliang Zhou; Junning Chen (Microelectron. J., 2025)

Real-time bit-line leakage balance circuit with four-input low-offset SA considering threshold voltage for SRAM stability design. - Chunyu Peng; Wei Hu; Hao Zheng; Wenjuan Lu; Chenghu Dai; Xiulong Wu; Zhiting Lin; Junning Chen (Int. J. Circuit Theory Appl., 2025)