ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation. - Junnosuke Suzuki; Kota Ando; Kazutoshi Hirose; Kazushi Kawamura; Thiem Van Chu; Masato Motomura; Jaehoon Yu (CANDAR, 2020)

ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation. - Junnosuke Suzuki; Tomohiro Kaneko; Kota Ando; Kazutoshi Hirose; Kazushi Kawamura; Thiem Van Chu; Masato Motomura; Jaehoon Yu (Int. J. Netw. Comput., 2021)

Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet. - Kazutoshi Hirose; Jaehoon Yu; Kota Ando; Yasuyuki Okoshi; Ángel López García-Arias; Junnosuke Suzuki; Thiem Van Chu; Kazushi Kawamura; Masato Motomura (ISSCC, 2022)

A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations. - Mari Yasunaga; Junnosuke Suzuki; Masato Watanabe; Kazushi Kawamura; Thiem Van Chu; Jaehoon Yu; Masato Motomura (MCSoC, 2023)

Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge. - Junnosuke Suzuki; Jaehoon Yu; Mari Yasunaga; Ángel López García-Arias; Yasuyuki Okoshi; Shungo Kumazawa; Kota Ando; Kazushi Kawamura; Thiem Van Chu; Masato Motomura (VLSI Technology and Circuits, 2023)

Progressive Variable Precision DNN With Bitwise Ternary Accumulation. - Junnosuke Suzuki; Mari Yasunaga; Kazushi Kawamura; Thiem Van Chu; Masato Motomura (AICAS, 2024)

WhiteDwarf: 12.24 TFLOPS/W 40 nm Versatile Neural Inference Engine for Ultra-Compact Execution of CNNs and MLPs Through Triple Unstructured Sparsity Exploitation and Triple Model Compression. - Yasuyuki Okoshi; Ángel López García-Arias; Jaehoon Yu; Junnosuke Suzuki; Hikari Otsuka; Thiem Van Chu; Kazushi Kawamura; Daichi Fujiki; Masato Motomura (A-SSCC, 2024)

High Throughput Datapath Design for Vision Permutator FPGA Accelerator. - Mari Yasunaga; Junnosuke Suzuki; Masato Watanabe; Kazushi Kawamura; Thiem Van Chu; Masato Motomura (ICCE, 2024)

Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision. - Junnosuke Suzuki; Jaehoon Yu; Mari Yasunaga; Ángel López García-Arias; Yasuyuki Okoshi; Shungo Kumazawa; Kota Ando; Kazushi Kawamura; Thiem Van Chu; Masato Motomura (IEEE Access, 2024)

WhiteDwarf: A Holistic Co-Design Approach to Ultra-Compact Neural Inference Acceleration. - Ángel López García-Arias; Yasuyuki Okoshi; Jaehoon Yu; Junnosuke Suzuki; Hikari Otsuka; Kazushi Kawamura; Thiem Van Chu; Daichi Fujiki; Masato Motomura (IEEE Access, 2025)