A Wireline Transceiver With 3-bit per Symbol Using Common-Mode NRZ and Differential-Mode PAM-4 Signaling Techniques. - Jincheol Sim; Jonghyuck Choi; Youngwook Kwon; Seungwoo Park; Seongcheol Kim; Changmin Sim; Hwaseok Shin; Junseob So; Seonbeen Lee; Chulwoo Kim (IEEE J. Solid State Circuits, 2024)

Single-Ended PAM-4 Transmitters With Data Bus Inversion and ZQ Calibration for High-Speed Memory Interfaces. - Seongcheol Kim; Jincheol Sim; Yoonjae Choi; Jonghyuck Choi; Youngwook Kwon; Seungwoo Park; Changmin Sim; Junseob So; Taehyeong Park; Chulwoo Kim (IEEE J. Solid State Circuits, 2024)

A 0.458-pJ/bit 24-Gb/s/pin Capacitively Driven PAM-4 Transceiver With PAM-Based Crosstalk Cancellation for High-Density Die-to-Die Interfaces. - Seongcheol Kim; Changmin Sim; Jincheol Sim; Jonghyuck Choi; Youngwook Kwon; Seungwoo Park; Junseob So; Hwaseok Shin; Seonbeen Lee; Chulwoo Kim (IEEE J. Solid State Circuits, 2024)

22.5 A 0.3pJ/b 32Gb/s/Pin Single-Ended PAM-4 Receiver with a Delay-Less Capacitive-Feedback Equalizer. - Junseob So; Youngwook Kwon; Seungwoo Park; Seongcheol Kim; Changmin Sim; Hwaseok Shin; Seonbeen Lee; Taehwan Kim; Chulwoo Kim (ISSCC, 2025)

A 10 Gb/s Single-Ended Receiver Using Time Gap Sense Amplifier for Next-Generation HBM. - Taehwan Kim; Changmin Sim; Seungwoo Park; Jinwoo Park; Seongcheol Kim; Hwaseok Shin; Junseob So; Seonbeen Lee; Youngwook Kwon; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A 28-Gb/s Single-Ended PAM-4 Transceiver With Active-Inductor Equalizer and Amplitude- Detection LSB Decoder for Memory Interfaces. - Hwaseok Shin; Hyoshin Kang; Yoonjae Choi; Jincheol Sim; Jonghyuck Choi; Youngwook Kwon; Seungwoo Park; Seongcheol Kim; Changmin Sim; Junseob So; Taehwan Kim; Chulwoo Kim (IEEE Trans. Very Large Scale Integr. Syst., 2025)