A MDLL-based multi-phase clock multiplier. - Junsub Yoon; Jongsun Kim (ISOCC, 2016)

A low-power SerDes for high-speed on-chip networks. - Dongjun Park; Junsub Yoon; Jongsun Kim (ISOCC, 2017)

A fast-locking harmonic-free digital DLL for DDR3 and DDR4 SDRAMs. - Junsub Yoon; Seo Weon Heo; Jongsun Kim (IEICE Electron. Express, 2017)

A Reflection and Crosstalk Canceling Continuous-Time Linear Equalizer for High-Speed DDR SDRAM. - Seunghwan Hong; Chang-Hyun Bae; Yoo-Chang Sung; Jaewoong Kim; Junsub Yoon; Sangwoo Kim; Jin-Hyeok Baek; Cheongryong Cho; Useung Shin; Sang-Kyeom Kim; Hwan-Chul Jung; Ho-Jun Chang; et al. (VLSI Circuits, 2021)

A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL. - Daehyun Kwon; Heon Su Jeong; Jaemin Choi; Wijong Kim; Jae Woong Kim; Junsub Yoon; Jungmin Choi; Sanguk Lee; Hyunsub Norbert Rie; Jin-Il Lee; Jongbum Lee; Taeseong Jang; et al. (ISSCC, 2023)

13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process. - IkJoon Choi; Seunghwan Hong; Kihyun Kim; Jeongsik Hwang; Seunghan Woo; Young-Sang Kim; Cheongryong Cho; Eun-Young Lee; Hun-Jae Lee; Min-Su Jung; Hee-Yun Jung; Ju-Seong Hwang; et al. (ISSCC, 2024)