A polynomial-time custom instruction identification algorithm based on dynamic programming. - Junwhan Ahn; Imyong Lee; Kiyoung Choi (ASP-DAC, 2011)

An efficient algorithm for isomorphism-aware custom instruction identification for extensible processors. - Junwhan Ahn; Kiyoung Choi (CODES+ISSS, 2011)

Lower-bits cache for low power STT-RAM caches. - Junwhan Ahn; Kiyoung Choi (ISCAS, 2012)

A Memetic Quantum-Inspired Evolutionary Algorithm for circuit bipartitioning problem. - Dongwoo Lee; Junwhan Ahn; Kiyoung Choi (ISOCC, 2012)

Resource-shared custom instruction generation under performance/area constraints. - Di Wu; Junwhan Ahn; Imyong Lee; Kiyoung Choi (ISSoC, 2012)

Selectively protecting error-correcting code for area-efficient and reliable STT-RAM caches. - Junwhan Ahn; Sungjoo Yoo; Kiyoung Choi (ASP-DAC, 2013)

Write intensity prediction for energy-efficient non-volatile caches. - Junwhan Ahn; Sungjoo Yoo; Kiyoung Choi (ISLPED, 2013)

Power-Efficient Predication Techniques for Acceleration of Control Flow Execution on CGRA. - Kyuseung Han; Junwhan Ahn; Kiyoung Choi (ACM Trans. Archit. Code Optim., 2013)

Isomorphism-Aware Identification of Custom Instructions With I/O Serialization. - Junwhan Ahn; Kiyoung Choi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Dynamic Power Management of Off-Chip Links for Hybrid Memory Cubes. - Junwhan Ahn; Sungjoo Yoo; Kiyoung Choi (DAC, 2014)

DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture. - Junwhan Ahn; Sungjoo Yoo; Kiyoung Choi (HPCA, 2014)

LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM Technology. - Junwhan Ahn; Kiyoung Choi (IEEE Trans. Very Large Scale Integr. Syst., 2014)

THOR: Orchestrated thermal management of cores and networks in 3D many-core architectures. - Jinho Lee; Junwhan Ahn; Kiyoung Choi; Kyungsu Kang (ASP-DAC, 2015)

A tiny-capacitor-backed non-volatile buffer to reduce storage writes in smartphones. - Mungyu Son; Junwhan Ahn; Sungjoo Yoo (CODES+ISSS, 2015)

Memory fast-forward: a low cost special function unit to enhance energy efficiency in GPU for big data processing. - Eunhyeok Park; Junwhan Ahn; Sungpack Hong; Sungjoo Yoo; Sunggu Lee (DATE, 2015)

A scalable processing-in-memory accelerator for parallel graph processing. - Junwhan Ahn; Sungpack Hong; Sungjoo Yoo; Onur Mutlu; Kiyoung Choi (ISCA, 2015)

PIM-enabled instructions: a low-overhead, locality-aware processing-in-memory architecture. - Junwhan Ahn; Sungjoo Yoo; Onur Mutlu; Kiyoung Choi (ISCA, 2015)

Energy-efficient exclusive last-level hybrid caches consisting of SRAM and STT-RAM. - Namhyung Kim; Junwhan Ahn; Woong Seo; Kiyoung Choi (VLSI-SoC, 2015)

Locality-aware vertex scheduling for GPU-based graph computation. - Hyunsun Park; Junwhan Ahn; Eunhyeok Park; Sungjoo Yoo (VLSI-SoC, 2015)

Zero and data reuse-aware fast convolution for deep neural networks on GPU. - Hyunsun Park; Dongyoung Kim; Junwhan Ahn; Sungjoo Yoo (CODES+ISSS, 2016)

AIM: Energy-Efficient Aggregation Inside the Memory Hierarchy. - Junwhan Ahn; Sungjoo Yoo; Kiyoung Choi (ACM Trans. Archit. Code Optim., 2016)

Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture. - Junwhan Ahn; Sungjoo Yoo; Kiyoung Choi (IEEE Trans. Computers, 2016)

Differential Write-Conscious Software Design on Phase-Change Memory: An SQLite Case Study. - Sungkwang Lee; Taemin Lee; Hyunsun Park; Junwhan Ahn; Sungjoo Yoo; Youjip Won; Sunggu Lee (ACM Trans. Design Autom. Electr. Syst., 2016)

Low-Power Hybrid Memory Cubes With Link Power Management and Two-Level Prefetching. - Junwhan Ahn; Sungjoo Yoo; Kiyoung Choi (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Weighted-Entropy-Based Quantization for Deep Neural Networks. - Eunhyeok Park; Junwhan Ahn; Sungjoo Yoo (CVPR, 2017)

Making DRAM Stronger Against Row Hammering. - Mungyu Son; Hyunsun Park; Junwhan Ahn; Sungjoo Yoo (DAC, 2017)

A novel zero weight/activation-aware hardware architecture of convolutional neural network. - Dongyoung Kim; Junwhan Ahn; Sungjoo Yoo (DATE, 2017)

ZeNA: Zero-Aware Neural Network Accelerator. - Dongyoung Kim; Junwhan Ahn; Sungjoo Yoo (IEEE Des. Test, 2018)

Benzene: An Energy-Efficient Distributed Hybrid Cache Architecture for Manycore Systems. - Namhyung Kim; Junwhan Ahn; Kiyoung Choi; Daniel Sánchez 003; Donghoon Yoo; Soojung Ryu (ACM Trans. Archit. Code Optim., 2018)

Nonvolatile Write Buffer-Based Journaling Bypass for Storage Write Reduction in Mobile Devices. - Mungyu Son; Junwhan Ahn; Sungjoo Yoo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Software-Defined Far Memory in Warehouse-Scale Computers. - H. Andrés Lagar-Cavilla; Junwhan Ahn; Suleiman Souhlal; Neha Agarwal; Radoslaw Burny; Shakeel Butt; Jichuan Chang; Ashwin Chaugule; Nan Deng; Junaid Shahid; Greg Thelen; Kamil Adam Yurtsever; et al. (ASPLOS, 2019)

An Imitation Learning Approach for Cache Replacement. - Evan Zheran Liu; Milad Hashemi; Kevin Swersky; Parthasarathy Ranganathan; Junwhan Ahn (ICML, 2020)

PaLM 2 Technical Report. - Rohan Anil; Andrew M. Dai; Orhan Firat; Melvin Johnson; Dmitry Lepikhin; Alexandre Passos; Siamak Shakeri; Emanuel Taropa; Paige Bailey; Zhifeng Chen; Eric Chu; Jonathan H. Clark; et al. (CoRR, 2023)

Retrospective: A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing. - Junwhan Ahn; Sungpack Hong; Sungjoo Yoo; Onur Mutlu; Kiyoung Choi (CoRR, 2023)