A CMOS gate array with dynamic-termination GTL I/O circuits. - Junya Kudoh; Toshiro Takahashi; Yukio Umada; Masaharu Kimura; Shigeru Yamamoto; Youichi Ito (ICCD, 1995)

Complex Bandpass DeltaSigmaAD Modulator Architecture without I, Q-Path Crossing Layout. - Hao San; Akira Hayakawa; Yoshitaka Jingu; Hiroki Wada; Hiroyuki Hagiwara; Kazuyuki Kobayashi; Haruo Kobayashi 001; Tatsuji Matsuura; Kouichi Yahagi; Junya Kudoh; Hideo Nakane; Masao Hotta; et al. (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

1-GHz Input bandwidth 6-bit under-sampling A/D converter for UWB-IR receiver. - Tatsuo Nakagawa; Tatsuji Matsuura; Eiki Imaizumi; Junya Kudoh; Goichi Ono; Masayuki Miyazaki; Akira Maeki; Yuji Ogata; Shinsuke Kobayashi; Noboru Koshizuka; Ken Sakamura (ESSCIRC, 2007)

A Second-Order Multibit Complex Bandpass DeltaSigmaAD Modulator with I, Q Dynamic Matching and DWA Algorithm. - Hao San; Yoshitaka Jingu; Hiroki Wada; Hiroyuki Hagiwara; Akira Hayakawa; Haruo Kobayashi 001; Tatsuji Matsuura; Kouichi Yahagi; Junya Kudoh; Hideo Nakane; Masao Hotta; Toshiro Tsukada; et al. (IEICE Trans. Electron., 2007)

1-GHz Input Bandwidth Under-Sampling A/D Converter with Dynamic Current Reduction Comparator for UWB-IR Receiver. - Tatsuo Nakagawa; Tatsuji Matsuura; Eiki Imaizumi; Junya Kudoh; Goichi Ono; Masayuki Miyazaki (IEICE Trans. Electron., 2009)