Regrasping behavior and object transition generated by EP. - Yasuhisa Hasegawa; Junya Matsuno; Toshio Fukuda (CEC, 2000)

Regrasping Behavior Generation for Rectangular Solid Object. - Yasuhisa Hasegawa; Junya Matsuno; Toshio Fukuda (ICRA, 2000)

Balanced Three-Phase Active-RC Tow-Thomas Biquad Complex Filter for Wireless Communication Systems. - Junya Matsuno; Hiroki Sato; Akira Hyogo; Keitaro Sekine (IEICE Trans. Electron., 2008)

A 7-bit 1.5-GS/s time-interleaved SAR ADC with dynamic track-and-hold amplifier. - Ippei Akita; Masanori Furuta; Junya Matsuno; Tetsuro Itakura (A-SSCC, 2011)

Harmonic Signal Rejection Schemes of Polyphase Downconverters. - Takafumi Yamaji; Hiroshi Tanimoto; Junya Matsuno; Tetsuro Itakura (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

All-digital background calibration for time-interleaved ADC using pseudo aliasing signal. - Junya Matsuno; Takafumi Yamaji; Masanori Furuta; Tetsuro Itakura (ISCAS, 2012)

A 3-GS/s 5-bit Flash ADC with wideband input buffer amplifier. - Junya Matsuno; Masahiro Hosoya; Masanori Furuta; Tetsuro Itakura (VLSI-DAT, 2013)

A 36-mW 1.5-GS/s 7-Bit Time-Interleaved SAR ADC Using Source Follower Based Track-and-Hold Circuit in 65-nm CMOS. - Masanori Furuta; Ippei Akita; Junya Matsuno; Tetsuro Itakura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

All-Digital Background Calibration Technique for Time-Interleaved ADC Using Pseudo Aliasing Signal. - Junya Matsuno; Takafumi Yamaji; Masanori Furuta; Tetsuro Itakura (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication. - Shigehito Saigusa; Toshiya Mitomo; Hidenori Okuni; Masahiro Hosoya; Akihide Sai; Shusuke Kawai; Tong Wang 018; Masanori Furuta; Kei Shiraishi; Koichiro Ban; Seiichiro Horikawa; Tomoya Tandai; et al. (ISSCC, 2014)

A Wide Bandwidth Analog Baseband Circuit for 60-GHz Proximity Wireless Communication Receiver in 65-nm CMOS. - Masanori Furuta; Hidenori Okuni; Masahiro Hosoya; Akihide Sai; Junya Matsuno; Shigehito Saigusa; Tetsuro Itakura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

A power-scalable zero-crossing-based amplifier using inverter-based zero-crossing detector with CMFB. - Junya Matsuno; Daisuke Kurose; Tomohiko Sugimoto; Hirotomo Ishii; Masanori Furuta; Tetsuro Itakura (ISCAS, 2016)

A Replica-Amp Gain Enhancement Technique for an Operational Amplifier with Low Mismatch Sensitivity and High Voltage Swing. - Junya Matsuno; Masanori Furuta; Tetsuro Itakura; Tatsuji Matsuura; Akira Hyogo (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

30.4 A 1Tb 3b/Cell 3D-Flash Memory in a 170+ Word-Line-Layer Technology. - Tsutomu Higuchi; Takuyo Kodama; Koji Kato; Ryo Fukuda; Naoya Tokiwa; Mitsuhiro Abe; Teruo Takagiwa; Yuki Shimizu; Junji Musha; Katsuaki Sakurai; Jumpei Sato; Tetsuaki Utsumi; et al. (ISSCC, 2021)

A 1Tb 3b/cell 3D-Flash Memory with a 29%-Improved-Energy-Efficiency Read Operation and 4.8Gb/s Power-Isolated Low-Tapped-Termination I/Os. - Kosuke Yanagidaira; Mario Sako; Yasuhiro Hirashima; Junya Matsuno; Yumi Higashi; Yutaka Shimizu; Akihiro Imamoto; Kazuaki Kawaguchi; Koji Tabata; Takeshi Nakano; Yusuke Ochi; Hiroaki Hoshino; et al. (ISSCC, 2025)